The paper describes and compares three different designs for a high-speed two's-complement, fullyserial tree multiplier, the first of which uses a correction technique, the second Booth's algorithm, and the third employs sign extension. All three designs, each of which possess advantages for different applications, may be clocked at the ceiling frequency determined by the delay through an adder and a flip-flop. Each design was simulated functionally at the gate level, an exercise that revealed several shortcomings and redundancies in what had been considered to be an optimal design. The importance of simulation for design verification in such cases is stressed and a straightforward method for accomplishing it, based on a synchronousstate machine approach and using a general-purpose language (Pascal), is presented.
IntroductionWith the recent growth of interest in digital communication, serial-processing techniques have become popular for analysing and manipulating word-formatted serial digital information. In particular, serial correlation may be employed for the insertion of control bits to monitor and correct codes [1], for the insertion of word and frame synchronisation information [1] and for data scrambling and unscrambling [2]. The majority of such correlation techniques which are currently in use employ parallel computation, but the ability to process 'on the fly' without having to resort to parallel-to-serial and serial-to-parallel conversion has obvious advantages. Several series/parallel multiplier chips are available commercially, such as the Am25LS14 [3], which is a cascadable 8-bit by 1-bit multiplier, where the multiplier is presented in parallel and the multiplicand bits are supplied serially. The whole operation requires 2n clock pulses where n is the word length. Such multipliers find use in applications such as scaling by a constant, but for the correlation applications such as those mentioned above, if fully serial processing is desired, then a multiplier where both multiplier and multiplicand are presented serially is required; and to this end the serial tree multiplier [4] is particularly suitable.The design presented in Reference 4, however, handles unsigned numbers only, and this paper considers three different ways in which the serial tree multiplier may be modified to handle two's-complement numbers.Each of the designs is then subjected to a rigorous functional simulation at the gate level, an exercise that revealed several shortcomings and redundances in what had been originally considered to be a correct and optimal design. The method used involves modelling the circuit as a synchronous-state machine using a general-purpose highlevel language -in this case Pascal -and exercising the model for all possible input combinations.One possible reason why design verification through functional simulation is not more widely used is the deterrent of having to learn and become familiar with a new language -and indeed the choice of language from the numerous simulation languages that exist. This pa...
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