A dielectric-defined process for the formation of T-gate field-effect transistors

Metze, G.; Bass, J.F.; Lee, T.T.; Porter, David H.; Carlson, H.; Laux, P.E.

doi:10.1109/75.84586

Cited by 6 publications

(3 citation statements)

References 2 publications

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“…Multiple field plates have shown a very promising way to address these issues, by alleviating the peak electric field at the edge of the gate [2]. While recessed dielectrics have been used in the past [4]- [8] to achieve field-plating and t-gate structures, the shaping of the dielectric during the recess process to create a slant field plate has the advantage of defining a gate with an integrated field plate optimized for high-voltage applications with a single lithography step.…”

Section: Introductionmentioning

confidence: 99%

High Breakdown Voltage Achieved on AlGaN/GaN HEMTs With Integrated Slant Field Plates

Dora

Chakraborty

McCarthy

et al. 2006

IEEE Electron Device Lett.

397

211

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A self-aligned "slant-field-plate" technology is presented as an improvement over the discrete multiple field plates for high breakdown voltage AlGaN/GaN HEMTs. Devices were tested in Fluorinert to eliminate the breakdown of air, which was identified to limit the breakdown voltage in AlGaN/GaN HEMTs. A single integrated field plate, which is self-aligned with the gate, is shown to support more than a kilovolt breakdown voltage (V br up to 1900 V was measured with Fluorinert). Devices made with this technology show a good large signal-frequency behavior. Various issues regarding breakdown measurements and interpretation of measurement results are presented.Index Terms-Breakdown voltage, field plate, GaN, high electron mobility transistor (HEMT).

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Section: Introductionmentioning

confidence: 99%

High Breakdown Voltage Achieved on AlGaN/GaN HEMTs With Integrated Slant Field Plates

Dora

Chakraborty

McCarthy

et al. 2006

IEEE Electron Device Lett.

397

211

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“…Regarding this aspect ratio, the dielectric-defined process is superior to the multiresist process because it inherently decouples the formation of the small gate foot from the much larger top portion of the gate. 9 In the Dielectric-defined T-shaped gate process shown in Fig. 3, dielectric layer of 50-nm thick Si 3 N 4 or 100-nm thick SiO 2 was deposited by PECVD on top of substrates separately in our experiments.…”

Section: Introductionmentioning

confidence: 99%

Femtosecond laser lithography technique for submicron <inline-formula><math display="inline" overflow="scroll"><mrow><mi>T</mi></mrow></math></inline-formula>-gate fabrication on positive photoresist

et al. 2012

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Femtosecond lasers have been found suitable for maskless photolithography with submicron resolution, which is very attractive for solving the problem of high photomask cost. Direct femtosecond laser writing of lithographic patterns is reported with submicron feature width on thin positive photoresist film. We use a scanning electron microscope to investigate the feature sizes of femtosecond laser lithography, which are determined by the incident laser power, the number of scan times and the substrate materials. Submicron T -shaped gates have been fabricated using a two-step process of femtosecond laser lithography where the gate foot and head can be separately defined on positive AZ4620 photoresist film. This work has led to the stable fabrication of sub-300 nm T -gates on the samples of GaN on sapphire substrate and AlGaN/GaN on Si substrate.

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“…[7][8][9] In still other methods, T-gate profiles have been created by etching the stem section into an oxide or nitride film, followed by a bi-layer lift-off process to create the cap. 10 Each method however has important drawbacks which make it unsuitable for manufacturing. E-beam systems offer very high resolution but suffer from very low throughput.…”

Section: Introductionmentioning

confidence: 99%

Bilayer and trilayer lift-off processing for i-line and DUV lithography

et al. 2002

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Lift-off resist processing has been used for a variety of applications as a way of patterning metal layers using additive deposition methods. Many different processes have been used for this purpose, each involving either single or multiple layers of resist which are processed to form a reentrant profile. In this study, we examine two specific applications where lift-off processing is especially challenging. In the first case, a high resolution i-line lift-off process was needed for an application having severe surface topography caused by thick surrounding ohmic structures. Conventional bi-layer resist processing provided poor critical dimension control due to adjacent reflective surfaces and swing effects caused by resist thickness non-uniformity. A solution was found by incorporating a developable anti-reflective coating into the resist stack to reduce reflectance and resulting swing effects. The result was a lift-off process with high resolution used to image gate trenches over severe topology with critical dimension control maintained. The second application involved creating a T-gate profile using conventional optical lithography methods and modern positive DUV resists. Problems related to interlayer mixing and dissolution were overcome by introducing a photostabilization process to harden the stem layer and maintain its fidelity during the coating of subsequent resist layers. The result was an all optical, positive DUV tri-layer resist stack performed using two separate optical exposures, which produced a 200 nm T-shaped gate structure.

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A dielectric-defined process for the formation of T-gate field-effect transistors

Cited by 6 publications

References 2 publications

High Breakdown Voltage Achieved on AlGaN/GaN HEMTs With Integrated Slant Field Plates

High Breakdown Voltage Achieved on AlGaN/GaN HEMTs With Integrated Slant Field Plates

Femtosecond laser lithography technique for submicron <inline-formula><math display="inline" overflow="scroll"><mrow><mi>T</mi></mrow></math></inline-formula>-gate fabrication on positive photoresist

Bilayer and trilayer lift-off processing for i-line and DUV lithography

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