A detailed and flexible cycle-accurate Network-on-Chip simulator

Jiang, Nan; Becker, Daniel U.; Michelogiannakis, George; Balfour, James; Towles, Brian; Shaw, David E.; Kim, John; Dally, William J.

doi:10.1109/ispass.2013.6557149

Cited by 572 publications

(188 citation statements)

References 30 publications

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“…We perform full-system simulation using a cycle-accurate x86 simulator, FeS2 [6]; the network is simulated with Booksim [3]. The configuration is listed in Table I.…”

Section: Resultsmentioning

confidence: 99%

Accelerating network-on-chip simulation via sampling

Dai

Jerger

2014

2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Abstract-Architectural complexity continues to grow as we consider the large design space of multiple cores, cache architectures, networks-on-chip and memory controllers for emerging architectures. Simulators are growing in complexity to reflect each of these system components. However, many full-system simulators fail to take advantage of the underlying hardware resources such as multiple cores; as a result, simulation times have grown significantly in recent years. Long turnaround times limit the range and depth of design space exploration that is tractable.Communication has emerged as a first class design consideration and has led to significant research into networks-on-chip (NoC). The NoC is yet another component of the architecture that must be faithfully modeled in simulation. Given its importance, we focus on accelerating NoC simulation through the use of sampling techniques; sampling can provide both accurate results and fast evaluation. We propose NoCLabs and NoCPoint, two sampling methodologies utilizing statistical sampling theory and traffic phase behavior, respectively. Experimental results show that our proposed NoCLabs and NoCPoint estimate NoC performance with an average error of 5% while achieving one order of magnitude speedup on average. I. INTRODUCTIONAs the number of cores in contemporary processors continues to scale, the criticality of Network-on-Chip (NoC) design to overall performance increases accordingly. NoC designers rely heavily on full-system simulation to faithfully evaluate their designs. In full-system simulation running multithread applications, the interaction between applications, cache coherence protocols and the network is fully exercised; the performance of new designs is accurately evaluated.Although full-system simulation enjoys the benefit of high fidelity, it suffers from prohibitively long turnaround times. Sampled full-system simulation [2], [5], [7], [9] is an effective technique to reduce simulation turnaround times for single-, multi-threaded and multiprogrammed applications. In sampled full-system simulation, only a small but representative portion of the application is simulated in detail. Performance metrics measured with the sampled application are used to estimate the true values of those metrics; the unsampled intervals are either fast forwarded using functional simulation or skipped entirely. Existing work applies to a wide range of applications (single or multi-threaded) and architectures (homogeneous or heterogeneous); however, they mainly focus on evaluating micro-architecture designs, and report metrics such as CPI (single-thread and multiprogrammed applications) or run time (multi-thread applications). To the best of our knowledge, there is no existing work exploring sampling methodologies for NoC simulation. In this paper, we introduce two sampling methodologies for NoC simulation: NoCLabs and NoCPoint.

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“…We perform full-system simulation using a cycle-accurate x86 simulator, FeS2 [6]; the network is simulated with Booksim [3]. The configuration is listed in Table I.…”

Section: Resultsmentioning

confidence: 99%

Accelerating network-on-chip simulation via sampling

Dai

Jerger

2014

2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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“…We use a heavily-modified version of the Booksim network simulator to model a local-store architecture similar to STI Cell [62] including processors, memory controllers, and local storage [34]. Initially we simulate writes and synchronous reads operations of single HTAs.…”

Section: Methodsmentioning

confidence: 99%

Collective Memory Transfers for Multi-Core Chips

Williams¹,

Shalf²

2013

Self Cite

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“…These tools are used either to evaluate the characteristics, functions, power consumption and performances of the NoC design (e.g. [54,60]), or to explore design space of reconfigurable NoCs (e.g. [30,41,62,64]).…”

Section: Simulatorsmentioning

confidence: 99%

A Survey on Reconfigurable System-on-Chips

Nguyen

Le-Van

Tran

2018

REV J. Electron. Commun.

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Abstract-The requirements for high performance and low power consumption are becoming more and more inevitable when designing modern embedded systems, especially for the next generation of multi-mode multimedia or communication standards. Ultra large-scale integration reconfigurable System-on-Chips (SoCs) have been proposed to achieve not only better performance and lower energy consumption but also higher flexibility and versatility in comparison with the conventional architectures. The unique characteristic of such systems is the integration of many types of heterogeneous reconfigurable processing fabrics based on a Network-on-Chip. This paper analyzes and emphasizes the key research trends of reconfigurable System-on-Chips (SoCs). Firstly, the emerging hardware architecture of SoCs is highlighted. Afterwards, the key issues of designing reconfigurable SoCs are discussed, with the focus on the challenges when designing reconfigurable hardware fabrics and reconfigurable Network-on-Chips. Finally, some state-of-the-art reconfigurable SoCs are briefly discussed.

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A detailed and flexible cycle-accurate Network-on-Chip simulator

Cited by 572 publications

References 30 publications

Accelerating network-on-chip simulation via sampling

Accelerating network-on-chip simulation via sampling

Collective Memory Transfers for Multi-Core Chips

A Survey on Reconfigurable System-on-Chips

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