Abstract-Architectural complexity continues to grow as we consider the large design space of multiple cores, cache architectures, networks-on-chip (NoC) and memory controllers. Simulators are growing in complexity to reflect these system components. However, many full-system simulators fail to utilize the underlying hardware resources such as multiple cores; consequently, simulation times have grown significantly. Long turnaround times limit the range and depth of design space exploration.Communication has emerged as a first class design consideration and has led to significant research into NoCs. NoC is yet another component of the architecture that must be faithfully modeled in simulation. Here, we focus on accelerating NoC simulation through the use of sampling techniques. We propose NoCLabs and NoCPoint, two sampling methodologies utilizing statistical sampling theory and traffic phase behavior, respectively. Experimental results show that NoCLabs and NoCPoint estimate NoC performance with an average error of 7% while achieving one order of magnitude speedup.
I. INTRODUCTIONAs the number of cores in contemporary processors continues to scale, the criticality of NoC design to overall performance increases accordingly. NoC designers are relying more heavily on full-system simulation to faithfully evaluate their designs. In full-system simulation, the interaction between applications and the NoC is fully exercised; the performance of new designs is accurately evaluated. Although full-system simulation enjoys the benefit of high fidelity, it suffers from prohibitively long turnaround times. Applications in full-system simulation experience up to 100,000× slow down compared to native execution [17] is an effective technique to reduce simulation turnaround times for single-, multi-threaded and multiprogrammed applications. In sampled full-system simulation, only a small but representative portion of the application is simulated in detail, the un-sampled intervals are fast forwarded. Existing work mainly focuses on evaluating micro-architecture designs, and report metrics such as CPI or application run time. To the best of our knowledge, there is no existing work exploring sampling methodologies for NoC simulation.Two major challenges exist for sampled NoC simulation 1 . First, NoC simulation focuses on different metrics compared to core simulation, so it requires a new sampling methodology.
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