A design of FIR filter using CSD with minimum number of registers

Suzuki, Kenichi; Ochi, H.; Kinjo, Shigenori

doi:10.1109/apcas.1996.569260

Cited by 11 publications

(6 citation statements)

References 2 publications

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“…A delay element is used to hold the output of the structural adder for one clock cycle and is typically implemented by delay Flip-Flop (FF). The authors of [9] suggest a ratio of 1 : 0.6 ∼ 0.8 for FA:FF. The TSMC 0.18µm standard cell library [10], which is used for our simulation, contains a variety of FFs with areas measured from 53.2 to 86.5µm 2 and a standard FA cell has an area of 69.9µm 2 .…”

Section: Proposed Structural Adder Optimizationmentioning

confidence: 99%

Optimization of structural adders in fixed coefficient transposed direct form FIR filters

Faust

Chang

2009

2009 IEEE International Symposium on Circuits and Systems

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Over the last two decades, fixed coefficient FIR filters were generally optimized by minimizing the number of adders required to implement the multiplier block in the transposed direct form filter structure. In this paper, an optimization method for the structural adders in the transposed tapped delay line is proposed. Although additional registers are required, an optimal trade-off can be made such that the overall combinational logic is reduced. For a majority of taps, the delay through the structural adder is shortened except for the last tap. The one full adder delay increase for the last optimized tap is tolerable as it does not fall in the critical path in most cases. The criterion for which area reduction is possible is analytically derived and an area reduction of up to 4.5% for the structural adder block of three benchmark filters is estimated theoretically. The saving is more prominent as the number of taps grows. Actual synthesis results obtained by Synopsys Design compiler with 0.18µm TSMC CMOS libraries show a total area reduction of up to 13.13% when combined with common subexpression elimination. In all examples, up to 11.96% of the total area saved were due to the reduction of structural adder costs by our proposed method.

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Section: Proposed Structural Adder Optimizationmentioning

confidence: 99%

Optimization of structural adders in fixed coefficient transposed direct form FIR filters

Faust

Chang

2009

2009 IEEE International Symposium on Circuits and Systems

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“…On the other hand, since only the input signals are delayed in the direct type, the bit widths of the registers can be minimized. It is understood that the initial gate number ratio of the transposition type to the direct type becomes 2.6 times when the initial gate number of the registers and adders necessary regardless of the search algorithm of a common pattern is compared considering up to their bit widths [4]. Thus, the direct-type architecture is adopted in this paper in order to decrease the overall filter gate number.…”

Section: Direct Type and Transposition Typementioning

confidence: 99%

VLSI design of a FIR filter using CSD representation with minimum number of registers

Suzuki

Ochi

Kinjo

2000

Electron. Comm. Jpn. Pt. III

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“…time delay elements). The gate number ratio of adders to registers is 1 : 0.6-0.8 [12]; therefore, in case of structure with many registers, the implementation cost cannot be reduced. In our previous paper [7] we have presented an improved horizontal and vertical CSE which is able to reduce the number of adders and registers, but the previous proposed method has needed a long simulation run-time in order to search all horizontal CS patterns.…”

Section: Introductionmentioning

confidence: 98%

A new horizontal and vertical common subexpression elimination method for multiple constant multiplication

Kato

Takahashi

Sekine

2009

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

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The common subexpression elimination (CSE) techniques address the issue of minimizing the number of adders needed to implement the multiple constant multiplication (MCM) blocks. In this paper, we propose a new CSE method using a combining horizontal and vertical technique. The proposed method searches firstly the frequency of higher order horizontal common subexpression, i.e., 3-5 bits, and then searches vertical. Our simulation results show that our method offers a good tradeoff between the implementation cost and the synthesis runtime in comparison with conventional methods.

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A design of FIR filter using CSD with minimum number of registers

Cited by 11 publications

References 2 publications

Optimization of structural adders in fixed coefficient transposed direct form FIR filters

Optimization of structural adders in fixed coefficient transposed direct form FIR filters

VLSI design of a FIR filter using CSD representation with minimum number of registers

A new horizontal and vertical common subexpression elimination method for multiple constant multiplication

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