A new horizontal and vertical common subexpression elimination method for multiple constant multiplication

Abstract

The common subexpression elimination (CSE) techniques address the issue of minimizing the number of adders needed to implement the multiple constant multiplication (MCM) blocks. In this paper, we propose a new CSE method using a combining horizontal and vertical technique. The proposed method searches firstly the frequency of higher order horizontal common subexpression, i.e., 3-5 bits, and then searches vertical. Our simulation results show that our method offers a good tradeoff between the implementation cost and the synthesis runtime in comparison with conventional methods.

Low-Cost Design of an FIR Filter by Using a Coefficient Mapping Method

“…The binary expressions for the coefficients can be found with the common subexpressions (CSs) between them. In previous researches [1][2][3][4][5][6][7][8][9], there are three common subexpression elimination (CSE) methods including horizontal, vertical, and mixed searching methods. The method in [1] uses CSD expressions [2] for the coefficients and uses horizontal searching algorithm to find the CSs including (1, 0, 1), (1, 0, −1), (1, 0, 0, 1), and (1, 0, 0, −1).…”

“…In [3,7], this method also uses CSD expressions, yet uses vertical search to find the CSs, including (1, −1) and (−1, 1). By modifying the vertical searching method in [8], the method in [4] first uses horizontal search to extract the CSs including (1, 0, 1), (1, 0, −1), (1, 0, 0, 1) and (1, 0, 0, −1), which is expressed in CSD format. Thereafter, this method performs a vertical search to extract the CSs, including (1, 0, 1) and (−1, 0, 1).…”

“…Besides finding two CSs with the same appearances, the method in [6] extracts the CS with a smaller bit width. A previous work [8] developed two methods for extracting the CSs in CSD format. The first method analyzes the CSs with 3-, 4-, and 5-bit by performing the statistics of their appearances.…”

“…The second method searches the coefficients up to down and extracts the CSs between them by using vertical search. The method in [9] proposes a rule in which the depth of logic gates cannot be increased by performing the horizontal search in the same way as in [4] and the vertical search in the same way as in [8].…”

“…The filter hardware consists of adders, subtractors, shifters, and registers. Many related works [1][2][3][4][5][6][7][8][9] attempt to reduce the number of these required components in filter implementation, especially for the optimization of coefficients' realization. Experimental results demonstrate that the proposed coefficient mapping method performs better than previous designs in terms of area ratio.…”