Low-Cost Design of an FIR Filter by Using a Coefficient Mapping Method

Chen, Mingchih; Wu, Hongyi

doi:10.1155/2013/495207

Cited by 3 publications

(4 citation statements)

References 13 publications

(40 reference statements)

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“…26 However, such implementations result in either low throughput per unit area or increased slice count. 27,28 In later works, [29][30][31][32] distributed arithmetic (DA)-based implementations are reported but are not suited for ASIC implementation and result in higher slice count when implemented on FPGA. 33 Literature reports architectures optimizing the adder structure to enhance the overall performance.…”

Section: Review Of Recent Literature On Hardware Implementation Of Fi...mentioning

confidence: 99%

“…In early literature, FIR filter are implemented using pipelined carry propagate and carry‐save multipliers and optimized using architecture folding, 24 common subexpression elimination (CSE), 25 and coefficient representation using canonical signed digit (CSD) 26 . However, such implementations result in either low throughput per unit area or increased slice count 27,28 . In later works, 29–32 distributed arithmetic (DA)‐based implementations are reported but are not suited for ASIC implementation and result in higher slice count when implemented on FPGA 33 …”

Section: Review Of Recent Literature On Hardware Implementation Of Fi...mentioning

confidence: 99%

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ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

Janwadkar,

Dhavse

2023

Circuit Theory & Apps

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The design of hand‐held portable devices for cardiovascular health monitoring based on the analysis of electrocardiogram (ECG) is a hot topic of research nowadays. Digital filters, possibly designed using digital multipliers, are a critical module in the design of such analysis systems. This paper presents the ASIC design of a 64th‐order digital low‐pass FIR filter to be used in ECG denoising applications. The FIR filter is optimized for usage in battery‐operated portable systems, wherein power consumption and on‐chip area are crucial parameters of concern. These challenges are met by employing a novel multiplier architecture, which we design by hybridizing the two popular digital multiplication algorithms, namely, the Vedic multiplication algorithm and the Wallace tree multiplication algorithm. The proposed multiplier consumes lower area and power consumption than either of the aforementioned conventional multiplication algorithms. This is established through FPGA‐based implementations on Artix‐7 FPGA, for the various wordlengths. The area and power optimizations are further exercised by two proposed techniques, namely, elimination of redundant multipliers, and power gating using the proposed zero‐detector circuit. RTL‐to‐GDSII flow has been completed using Cadence digital design and sign‐off tools for SCL 180 nm technology. The results indicate that the proposed filter architecture occupies 16.38% lower area and 79.58% lower power consumption than the contemporary designs described in the literature.

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Section: Review Of Recent Literature On Hardware Implementation Of Fi...mentioning

confidence: 99%

Section: Review Of Recent Literature On Hardware Implementation Of Fi...mentioning

confidence: 99%

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

Janwadkar,

Dhavse

2023

Circuit Theory & Apps

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“…To optimize the coefficients of the finite impulse response (FIR) filter, a new coefficient mapping technique is proposed in Chen and Wu (2013) to reduce cost and minimize the area of FIR filter design. The proposed mapping techniques involve four steps to reduce area, minimize cost and enhance the performance of the filter.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of pervasive DA based FIR filter and feeder register based multiplier for software definedradio networks

Kumar

Rangaraju

2021

IJPCC

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Purpose Digital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization. Design/methodology/approach The distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324. Findings The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively. Originality/value The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.

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“…To optimize the coefficients of the FIR filter, a new coefficient mapping technique is proposed in the study of Chen and YiWu (2013) to reduce cost and minimize the area of FIR filter design. The proposed mapping technique involves four steps to reduce area, minimize cost and enhance the performance of the filter.…”

Section: Introductionmentioning

confidence: 99%

Optimized DA-reconfigurable FIR filters for software defined radio channelizer applications

Murthy

Sridevi

2021

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Purpose In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters. Design/methodology/approach The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer. Findings Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively. Originality/value The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

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Low-Cost Design of an FIR Filter by Using a Coefficient Mapping Method

Cited by 3 publications

References 13 publications

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

Design and implementation of pervasive DA based FIR filter and feeder register based multiplier for software definedradio networks

Optimized DA-reconfigurable FIR filters for software defined radio channelizer applications

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