Optimization of structural adders in fixed coefficient transposed direct form FIR filters

Abstract

Over the last two decades, fixed coefficient FIR filters were generally optimized by minimizing the number of adders required to implement the multiplier block in the transposed direct form filter structure. In this paper, an optimization method for the structural adders in the transposed tapped delay line is proposed. Although additional registers are required, an optimal trade-off can be made such that the overall combinational logic is reduced. For a majority of taps, the delay through the structural adder is shortened except for the last tap. The one full adder delay increase for the last optimized tap is tolerable as it does not fall in the critical path in most cases. The criterion for which area reduction is possible is analytically derived and an area reduction of up to 4.5% for the structural adder block of three benchmark filters is estimated theoretically. The saving is more prominent as the number of taps grows. Actual synthesis results obtained by Synopsys Design compiler with 0.18µm TSMC CMOS libraries show a total area reduction of up to 13.13% when combined with common subexpression elimination. In all examples, up to 11.96% of the total area saved were due to the reduction of structural adder costs by our proposed method.

High-speed multiplierless Frequency Response Masking (FRM) FIR filters with reduced usage of hardware resources

“…Nevertheless, when the transposed structure is used in both, the model subfilter and its complementary pair, a huge amount of extra delay elements needs to be aggregated. It has been shown that delays have a hardware cost similar to adders [15]. Thus, the use of transposed structures leads to an inefficient implementation in terms of usage of hardware resources, which is translated into a high demand of chip area.…”

Efficient structural adder pipelining in transposed form FIR filters

“…However, more adders are required compared to multiplier blocks designed by CPAs for word lengths of coefficients larger than 9 bits [12]. Moreover, the use of the redundant carry-save representation The area optimization of SAs in transposed form FIR filters was first investigated by Faust and Chang in [13]. To the best of our knowledge, this is another pioneering work where pipelining of structural adders is considered.…”

Techniques for avoiding sign-extension in multiple constant multiplication

“…It was also shown that half adders could be completely removed by selecting a suitable sign of each partial result. In [17], a technique for reducing the number of full adder cells for the structural adders, the adders between the delay elements in Fig. 1, was proposed.…”