A delay efficient robust self-timed full adder

Abstract

Abstract-Addition forms the basis of digital computer systems. A gate level self-timed full adder design, utilizing a pre-defined set of gates, available in a commercial synchronous standard cell library is discussed in this paper. The proposed adder satisfies Seitz's weak-indication specifications and exhibits reduced data path delay in comparison with other existing adders, which satisfy the property of indication. In terms of power and area, it is competitive to the best of other self-timed adders.

Dual-Sum Single-Carry Self-Timed Adder Designs

“…A weakly indicating traditional single-sum singlecarry (SSSC) or single-bit adder based on [14] is referred to as proposed_SSSC in Tables 1 and 2. ST DSSC adder modules were realized based on [8], [9] and [10] as well and they are referred to as Seitz_DSSC, DIMS_DSSC and Toms_DSSC in the tabular columns.…”

“…Among the different ST adder realizations that pertain to [7] - [10] and [14], the weakly indicating single-bit full adder design based on [14] was found to exhibit minimum data path and function block delay. This is mainly due to the fast carry propagation resulting from weak-indication of carry outputs.…”

“…C-elements, which form the backbone of robust ST architectures, have been realized using standard library cells in our earlier work [14]. A C-element, also used as a latch, outputs logic high (low) only when all its inputs become logic high (low); otherwise they retain their existing state.…”

Self-timed full adder designs based on hybrid input encoding

“…The inputs are assumed to arrive from the environment and are fed to the adders every 30ns, 50ns and 20ns for the typical, worst and best case library specifications respectively. [3] 7100 Seitz_DRE (Weak) [3] 6276 Singh_DRE (Strong) [4] 7364 DIMS_DRE (Strong) [6] 8932 DIMS_DRE (Weak) [6] 9508 Folco et al_DRE (Weak) [7] 5476 Toms_DRE (Strong) [8] 6404 Proposed_DRE (Weak) [2] 5924 Toms_HIE (Strong) [8] 4868 Proposed_HIE_NRL (Weak) 3940 Proposed_HIE_RL (Weak) 4260…”

“…Although it is an attractive alternative to conventional digital logic design, it can be noticed that the vast majority of existing commercial EDA tools ideally support synchronous circuits. Therefore, in order to utilize the sophistication and advantages offered by industry-standard EDA tools and synchronous resources (standard cells), an attempt was made to realize ST logic (especially, a ST full adder design) and also validate them using the above in [2]. Additionally, realization of higher order C-elements functionality using standard cells was done, whilst preserving the property of indication (completion).…”