A degradation-free Cu/HSQ damascene technology using metal mask patterning and post-CMP cleaning by electrolytic ionized water

Aoki, Hidemitsu; Yamasaki, Shigeto; Usami, T.; Tsuchiya, Yumi; Ito, N.; Onodera, T.; Hayashi, Y.; Ueno, Katsuya; Gomi, H.; Aoto, Nahomi

doi:10.1109/iedm.1997.650497

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Cited by 9 publications

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“…Recently, low resistance Cu interconnects and low-k dielectric materials have been expected to solve this problem [2,3]. However, Cu interconnects formed by damascene process need some "highk" dielectric films: e.g.…”

Section: Introductionmentioning

confidence: 99%

The best combination of aluminum and copper interconnects for a high performance 0.18 μm CMOS logic device

Igarashi

Harada²,

Amishiro³

et al.

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)

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A high performance 0.18pm CMOS logic device has been developed with 0.15pm transistors and six-level interconnects. The multi-level interconnect system consists of a conventional process with A1 wire and a dual damascene process with Cu wire. 4-level AI interconnects with fine metal pitch are suitable for short distance wiring such as intra block cell to cell interconnects, whereas 2-level Cu interconnects with coarse metal pitch are used for long distance wiring such as mega block to block interconnects to achieve high-speed and high-density LSI devices.

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Section: Introductionmentioning

confidence: 99%