A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC

Hong, Hyeok-Ki; Kim, Wan; Kang, Hyun-Wook; Park, Sun‐Jae; Choi, Michael; Hojin, Park; Ryu, Seung‐Tak

doi:10.1109/jssc.2014.2364833

Cited by 83 publications

(20 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Then comparators' offsets are calibrated alternately and each comparator's calibration is operated every second cycle. The SAR Logic and data register of the designed ADC has been further enhanced by register-to-DAC direct control and domino-cell based pseduo-static dynamic register as proposed in [7].…”

Section: Proposed Adc Architecturementioning

confidence: 99%

“…Asynchronous clocking [6] allows the comparision time allocated to each bit to be adjusted by the comparator itself and avoids the high-speed clock's generation and distribution. M-bit per cycle SAR ADCs [7,8] quantize M-bits simultaneously with 2 M -1 comparators to increase conversion speed. But comparators mismatches should be resolved with calibrations and more capacitors DACs' areas cost.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 6 mW 325 MS/s 8 bit SAR ADC with background offset calibration

Zhu

Zhou

et al. 2017

IEICE Electron. Express

View full text Add to dashboard Cite

An 8-b single-channel successive approximation register (SAR) analog-to-digital converter (ADC) fabricated in 55 nm CMOS is proposed. With segmented prequantize and bypass digital-to-analog converter (DAC), the unnecessary switching of high weight capacitors are avoided. Two alternating comparators are utilized to reset the comparators completely without the sacrifice of conversion speed. A novel simple and low power background offset calibration technique is implemented. Operating at 325 MS/s, this ADC consumes 6 mW from 1.2 V supply, achieves SNDR of 43.6 dB and SFDR of 59.1 dB with 11-MHz input while occupying 0.011 mm 2 .

show abstract

Section: Proposed Adc Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 6 mW 325 MS/s 8 bit SAR ADC with background offset calibration

Zhu

Zhou

et al. 2017

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…One of the most popular ways to eliminate the comparator offset is to add an additional input pair with an adjustable DC input. The DC input required for the offset calibration can be generated in various ways [16], [18]- [20]. Among them, however, R-string based calibration [18] might not be an appropriate choice for low-power applications due to its static power consumption.…”

Section: B Gain-boosting Pre-amplifier For Low-noise Dynamic Comparatormentioning

confidence: 99%

A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC

Kim

Hong

Roh

et al. 2016

IEEE J. Solid-State Circuits

Self Cite

View full text Add to dashboard Cite

This paper presents an asynchronous SAR-assisted time-interleaved SAR (SATI-SAR) ADC as a suitable architecture in a low-supply-voltage condition. Settling-While-Conversion enabled by the Assist-ADC relaxes the DAC settling time requirement and makes it possible to insert a minimized capacitor shuffling logic with no speed penalty. A proposed gain-boosting dynamic pre-amplifier enhances the noise performance of the comparator and a self time-reference generation function is embedded in the pre-amplifier for a speed-enhanced asynchronous decision. A proposed dual-mode clock generator generates a low-jitter fixed-width sampling pulse for high-frequency operation while it generates a low-power-but-low-quality clock for low-frequency operation. With the dual-mode clock generator enabled, a prototype 65 nm CMOS 0.6 V 12 b 10 MS/s ADC achieves an ENOB of 10.4 at a Nyquist-rate input, and the peaks of DNL and INL are measured to be 0.24 LSB and 0.45 LSB, respectively. The FoM is 6.2 fJ/conversion-step with a power consumption of 83 µW. The ADC operates under the lowest supply voltage of 0.6 V among comparable designs with ENOBs over 10 and conversion rates over 1 MS/s. Index Terms-Asynchronous SAR ADC, gain-boosting dynamic comparator, low voltage, low-jitter clock, low-noise comparator, SAR-assisted time-interleaved SAR (SATI-SAR).

show abstract

“…Recently, there are quite a few low-power or high-performance SAR ADC circuits reported in literature [1][2][3][4][5][6][7][8][9][10]. Typically, SAR ADCs implement the binary search algorithm and require N conversion cycles to generate an N-bit digital output.…”

Section: Introductionmentioning

confidence: 99%

“…Multi-bits per cycle techniques have been used to reduce the total number of conversion cycles [1][2][3][4][5]. This is achieved by simultaneously comparing the ADC input with multiple levels by using multiple comparators.…”

Section: Introductionmentioning

confidence: 99%

A novel time and voltage based SAR ADC design with self-learning technique

Nagabhushana

Wang

2016

Proceedings of the 53rd Annual Design Automation Conference

View full text Add to dashboard Cite

This paper presents a novel time and voltage based technique for successive approximation register (SAR) analogto-digital converter (ADC) to improve the conversion speed. By taking advantage of the fact that at low supply voltage there will be a significant difference in comparator decision time for different input voltages, the proposed technique creates multiple auxiliary voltage levels for comparison and hence eliminates the need of additional comparators for acceleration as compared with the existing methods. In addition, a digital self-learning module is also presented, which calculates the uncertainty window required for bound update in the proposed method and thus adjusts to different process corners. To validate these concepts, a 10-bit SAR ADC is designed in 130nm CMOS process with 0.5V power supply voltage. The circuit operates in both conventional and proposed modes. Simulations show that the largest number of conversion cycles is 7, hence resulting in an acceleration of 30% over the conventional scheme, while the average number of cycles is 5.58. Simulation results also demonstrate that the proposed method does not affect accuracy. Both ADC operation modes achieve SNDR (signal-tonoise distortion ratio) of 59dB, corresponding to an ENOB (effective number of bits) of 9.5-bits.

show abstract

A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC

Cited by 83 publications

References 10 publications

A 6 mW 325 MS/s 8 bit SAR ADC with background offset calibration

A 6 mW 325 MS/s 8 bit SAR ADC with background offset calibration

A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC

A novel time and voltage based SAR ADC design with self-learning technique

Contact Info

Product

Resources

About