A 6 mW 325 MS/s 8 bit SAR ADC with background offset calibration

Zhu, Xiaoge; Wu, Danyu; Zhou, Lei; Ma, Chonghe; Wang, Dandan; Luan, Jian; Huang, Yinkun; Wu, Jin; Liu, Xinyu

doi:10.1587/elex.14.20170329

Cited by 4 publications

(2 citation statements)

References 12 publications

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“…The sub-ADC is implemented with 325 MS/s 8-bit SAR ADC [17], including fundamental building blocks, such as capacitive digital-to-analog converter (CDAC), comparators and control logic, as illustrated in Figure 4a. When CK ch,i becomes high, the switching transistor M 0 is turned on, and the channel begins to track the input signal.…”

Section: Asynchronous Timing Of Alternate Comparatorsmentioning

confidence: 99%

“…The sub-ADC is implemented with 325 MS/s 8-bit SAR ADC [17], including fundamental building blocks, such as capacitive digital-to-analog converter (CDAC), comparators and control logic, as illustrated in Figure 4a. If only one comparator is used in the SAR ADC, the comparator needs to be fully reset to avoid the residual effect from the previous conversion process, so the overall conversion speed is slowed down.…”

Section: Asynchronous Timing Of Alternate Comparatorsmentioning

confidence: 99%

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A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

et al. 2019

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This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock to suppress the time skew between channels. Based on the segmented pre-quantization and bypass switching scheme, double alternate comparators clocked asynchronously with background offset calibration are utilized in sub-channel SAR ADC to achieve high speed and low power. Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) of the ADC is above 38.2 dB up to 500 MHz input frequency and above 31.8 dB across the entire first Nyquist zone. The differential non-linearity (DNL) and integral non-linearity (INL) are +0.93/−0.85 LSB and +0.71/−0.91 LSB, respectively. The ADC consumes 60 mW from a 1.2 V supply, occupies an area of 400 μm × 550 μm, and exhibits a figure-of-merit (FoM) of 348 fJ/conversion-step.

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Section: Asynchronous Timing Of Alternate Comparatorsmentioning

confidence: 99%

“…The sub-ADC is implemented with 325 MS/s 8-bit SAR ADC [17], including fundamental building blocks, such as capacitive digital-to-analog converter (CDAC), comparators and control logic, as illustrated in Figure 4a. If only one comparator is used in the SAR ADC, the comparator needs to be fully reset to avoid the residual effect from the previous conversion process, so the overall conversion speed is slowed down.…”

Section: Asynchronous Timing Of Alternate Comparatorsmentioning

confidence: 99%

A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

et al. 2019

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A 700-MS/s 6-bit SAR ADC with partially active reference voltage buffer

Zhao

Yang

2018

IEICE Electron. Express

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This paper presents a 700-MS/s 6-bit SAR ADC with a novel on-chip reference voltage buffer in a 40-nm CMOS Low-Leakage (LL) process. The reference voltage buffer is partially active depending on the operation state of the SAR ADC. The large driving current is provided only when the Capacitive Digital-to-Analog Converter (CDAC) is settling. This approach achieves 42% power reduction for the reference voltage buffer, which helps to improve the Figure-

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A 16-bit 8-MS/s SAR ADC with a foreground calibration and hybrid-charge-supply power structure

Zhang

Qiu

Shan

et al. 2020

IEICE Electron. Express

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In this paper, a 16-bit 8-MS/s successive approximation register analog-to-digital converter (SAR ADC) with a foreground calibration technique is proposed. A nonbinary searching algorithm is adopted to speed up the conversion rate and overcome the incomplete settling of the reference voltage. A foreground calibration method with low-cost circuitry is implemented to detect the mismatch of the capacitor digital-to-analog converter in calibration mode and compensate for the output code in conversion mode. The simulation results show that the peak signal-to-noise and distortion (SNDR) and spurious free dynamic range (SFDR) are improved from 69.98 dB to 91.39 dB and 73.94 dB to 99.41 dB, respectively. Moreover, the proposed ADC uses a hybrid-charge-supply power structure. The sampling circuit operates at 3.3 V to maintain a wide dynamic range, the logic circuit operates at 1.2 V to decrease the conversion time and power consumption, and the total power consumption is 45 mW at 8 MS/s.

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A 6 mW 325 MS/s 8 bit SAR ADC with background offset calibration

Cited by 4 publications

References 12 publications

A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

A 700-MS/s 6-bit SAR ADC with partially active reference voltage buffer

A 16-bit 8-MS/s SAR ADC with a foreground calibration and hybrid-charge-supply power structure

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