A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC

Abstract

This paper presents an asynchronous SAR-assisted time-interleaved SAR (SATI-SAR) ADC as a suitable architecture in a low-supply-voltage condition. Settling-While-Conversion enabled by the Assist-ADC relaxes the DAC settling time requirement and makes it possible to insert a minimized capacitor shuffling logic with no speed penalty. A proposed gain-boosting dynamic pre-amplifier enhances the noise performance of the comparator and a self time-reference generation function is embedded in the pre-amplifier for a speed-enhanced asynchronous decision. A proposed dual-mode clock generator generates a low-jitter fixed-width sampling pulse for high-frequency operation while it generates a low-power-but-low-quality clock for low-frequency operation. With the dual-mode clock generator enabled, a prototype 65 nm CMOS 0.6 V 12 b 10 MS/s ADC achieves an ENOB of 10.4 at a Nyquist-rate input, and the peaks of DNL and INL are measured to be 0.24 LSB and 0.45 LSB, respectively. The FoM is 6.2 fJ/conversion-step with a power consumption of 83 µW. The ADC operates under the lowest supply voltage of 0.6 V among comparable designs with ENOBs over 10 and conversion rates over 1 MS/s. Index Terms-Asynchronous SAR ADC, gain-boosting dynamic comparator, low voltage, low-jitter clock, low-noise comparator, SAR-assisted time-interleaved SAR (SATI-SAR).

A Design of 8 fJ/Conversion-Step 10-bit 8MS/s Low Power Asynchronous SAR ADC for IEEE 802.15.1 IoT Sensor Based Applications

“…SAR ADCs are suitable for increasing scale-down technology and also can operate at a very low-power supply voltage. Excellent power efficiency and low analog complexity make the SAR ADC one of the best candidates for low energy applications [4]- [10].…”

“…A tri level switching scheme named as reverse V CM based scheme which maintains good linearity without any driving and accuracy requirements on V CM is represented in [6], and charge redistribution digital-to-analog converter (DAC) for the SAR ADC to reduce the area cost and power consumption and to promote the bandwidth is shown in [7]. For low supply voltage, asynchronous SAR assisted time-interleaved SAR ADC is considered in [10]. A dual-mode clock generator generates a low-jitter fixed-width sampling pulse for high-frequency operation while it generates a low-power-butlow-quality clock for low-frequency operation.…”

A low power 10 bit SAR ADC with variable threshold technique for biomedical applications

“…Physiological signals are the pure analog signals which are captured from the human body with transducers. The successive approximation register (SAR) type analog-to-digital converter (ADC) is an essential part in the analog signal processing [11][12][13][14][15][16][17][18]. SAR ADCs are available from 8 to 18 bits resolution with sampling rates up to 50 Msps [11,12].…”

A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique

“…In recent years, with the improvement of CMOS technology, successive approximation register (SAR) analog-todigital converters ADCs have been able to achieve sampling rates of several hundreds of MS/s with high power efficiency and small area [1,2,3,4,5,6,7,8,9,10]. Meanwhile, 8 to 12-bit SAR ADCs could reach sampling rates of hundreds or thousands MS/s and provide compact area and outstanding power efficiency [11,12,13,14,15,16,17,18,19,20,21,22]. Based on high performance SAR ADC, time-interleaved SAR ADCs (TI SAR ADC) are superior in aspects of highly scalable and power efficiency to advanced CMOS technology.…”