A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code

Widmer, A.X.; Franaszek, P. A.

doi:10.1147/rd.275.0440

Cited by 463 publications

(200 citation statements)

References 12 publications

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“…the powering blocks). FE-I4A's periphery consists of an End of Chip Logic block which organizes trigger propagation, pixel hit formatting and does temporary hit storage, a Phase Locked Loop (PLL) Clock Generator block which takes the 40 MHz LHC machine clock and generates the 160 MHz clock necessary for 160 Mb/s data transfer, a Data Output Block which does 8b10b [6] data encoding and 160 Mb/s serialization, a Command Decoder which decodes Level-1 Trigger commands as well as the Global Configuration (then held in Configuration Registers) and the Pixel Local Configuration (held in memories at pixel level), and DACs used to generate biases based on the values stored in the Configuration Registers. For testing of various powering options, FE-I4A contains 2 Shunt-LDO voltage regulators, a device based on a shunt transistor (for serial powering applications) with extra Low Drop-Out regulation capability (see [7]).…”

Section: Fe-i4a Peripherymentioning

confidence: 99%

FE-I4 pixel readout chip and IBL module

Barbero

Hemperek²,

Zivkovic³

et al. 2012

Proceedings of the 20th Anniversary International Workshop on Vertex Detectors — PoS(Vertex 2011)

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FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the "Insertable B-Layer" project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.

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Section: Fe-i4a Peripherymentioning

confidence: 99%

FE-I4 pixel readout chip and IBL module

Barbero

Hemperek²,

Zivkovic³

et al. 2012

Proceedings of the 20th Anniversary International Workshop on Vertex Detectors — PoS(Vertex 2011)

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“…• The Data Output Block takes the pixel data stored in the End of Chip logic FIFO and provides 8b10b encoding [12] before streaming out the encoded data at 160 Mb/s. The default output format for the FE-I4 data is 8b10b encoded, which should provide a data stream with proper engineering properties off-detector and in turn should ease clock reconstruction from the data stream.…”

Section: Materials Reduction For the Inner Pixel Layers And Consequencmentioning

confidence: 99%

Submission of the first full scale prototype chip for upgraded ATLAS pixel detector at LHC, FE-I4A

Barbero

Arutinov

Beccherle

et al. 2011

Nuclear Instruments and Methods in Physics Research Section A:

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A new ATLAS pixel chip FE-I4 is being developed for use in upgraded LHC luminosity environments, including the near-term Insertable B-Layer (IBL) upgrade. FE-I4 is designed in a 130 nm CMOS technology, presenting advantages in terms of radiation tolerance and digital logic density compared to the 0.25 µm CMOS technology used for the current ATLAS pixel IC, FE-I3. The FE-I4 architecture is based on an array of 80×336 pixels, each 50×250 µm 2 , consisting of analog and digital sections.In the summer 2010, a first full scale prototype FE-I4A was submitted for an engineering run. This IC features the full scale pixel array as well as the complex periphery of the future full-size FE-I4. The FE-I4A contains also various extra test features which should prove very useful for the chip characterization, but deviate from the needs for standard operation of the final FE-I4 for IBL. In this paper, focus will be brought to the various features implemented in the FE-I4A submission, while also underlining the main differences between the FE-I4A IC and the final FE-I4 as envisioned for IBL.Keywords: Pixel detector, ATLAS, upgrade, IBL, FE-I4 Scope of the project and introduction to FE-I4In these first years of operational experience with the LHC, the road to higher LHC luminosity is clearing up, allowing the detector communities to devise plans for detector upgrades.The ATLAS pixel detector will see two major phases of upgrade, phase I during the year 2016 shutdown, and phase II for the High Luminosity upgrade (HL-LHC) in 2020. For the phase I upgrade, the addition of a fourth layer to the pixel system with a smaller beam pipe is foreseen: This project is called the Insertable B-layer (IBL). For the HL-LHC upgrade, a new Inner Tracker will replace the existing one.The design of the FE-I4 has started when it was realized that the FE-I3 IC [2] presently used in the ATLAS 1 Corresponding author: barbero@physik.uni-bonn.de 2 Visitor from Laboratoire de l'Accélérateur Linéaire, Orsay, FR pixel detector [3] features an architecture which scales badly with hit rates higher than the ones expected for LHC full design luminosity. The FE-I3 is based on an architecture which requires transfer of every pixel hit down to data buffers belonging to the periphery of the IC. The pixel hit data fill these buffers until expiration of the trigger latency -typically of order 3 µs-before being transmitted for readout if triggered or, with much higher probability, erased if not triggered. The data transfer mechanism from the pixel to the periphery is time consuming and becomes highly inefficient at higher hit rates (for more information about hit recording inefficiencies at high hit rate in the current pixel FE and in FE-I4, see [4]).One of the first test chips submitted in the framework of the FE-I4 collaboration at the end of 2006 was an exploratory prototype analog array [5]. This test chip was tested in 2007 and is the basis of the present analog

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“…As seen in the original 5B/6B encoding given in ref. [1], the first four bits of encoded outputs (denoted as 'abcd') are not changed except the corresponding bits of input data 'ABCD' are either all zero's or all one's. In order to reduce the number of input patterns to consider the first four bits ('ABCD') are added.…”

Section: Fig 1 Block Diagram Of Proposed 8b/10b Encodermentioning

confidence: 99%

“…Also it provides a DC balance by trying to equalize the number of '0' and '1' in the data stream. Most popular, de facto standard, 8B/10B encoder is based on the scheme proposed by IBM [1]. However, the logic implemented based on the IBM's encoding table needs deep logic depths, which limits the operating speed.…”

Section: Introductionmentioning

confidence: 99%

High-speed 8B/10B encoder design using a simplified coding table

Kim

Shin

Kang

2008

IEICE Electron. Express

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This letter presents a high-speed 8B/10B encoder design using a simplified coding table. The proposed encoder also includes a modified disparity control block. Logic simulation and synthesis have been done for the performance verification. After synthesized with a CMOS 0.18 µm process, the proposed design shows the operating frequency of 343 MHz with no latency. The synthesized chip area is 1886 µm 2 with 189 logic gates. The proposed 8B/10B encoder shows the overall performance improvement compared to previous approaches.

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A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code

Abstract: Ewen et al. (54) (75) (73) (21) 22) (51) 52 58)

Cited by 463 publications

References 12 publications

FE-I4 pixel readout chip and IBL module

FE-I4 pixel readout chip and IBL module

Submission of the first full scale prototype chip for upgraded ATLAS pixel detector at LHC, FE-I4A

High-speed 8B/10B encoder design using a simplified coding table

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