A data aware 9T static random access memory cell for low power consumption and improved stability

Singh, Ajay Kumar; Seong, Mah Meng; Prabhu, C. M. R.

doi:10.1002/cta.1897

Cited by 8 publications

(6 citation statements)

References 25 publications

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“…The priority encoder depicted in Figure 5 is used as the input buffer to prevent different data bits stored in the same row. For example, the two write word lines WDA [20] and WDB [20] activate the same memory row "20," wherein the input data DA[5:0] = "11111" and DB[5:0] = "00000" are quite different. Then, the priority encoder sets the priority data input based on the RRU control signals (LDA[5:0], ADB[5:0]) to propagate to row "20," avoiding contention in the stored memory cells.…”

Section: Write Circuit Architecture and Timingmentioning

confidence: 99%

Design of memory Alias Table based on the SRAM 8T‐Cell

Abdel‐hafeez

Otoom

Quwaider

2022

Circuit Theory & Apps

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A memory Alias Table holds a major role in Register Renaming Unit (RRU), which is responsible for maintaining the translation between logical registers to physical registers under the given instruction(s). This work presents the design of the memory Alias Table based on the SRAM‐based 8T‐Cell with multiport write, read, and content‐address operations for two‐way three operands machine cycle. The design of the memory Alias Table of size 32‐row × 6‐bit has SRAM‐based CAM cell of type 21T‐Cell that comprises four‐read ports, two‐write ports, and two‐content‐address ports. The content‐address examines the register under‐test against all contents of the memory Alias Table in parallel and releases the associated match index address. Results show that the four read ports operate simultaneously within the half‐cycle, while the two write ports operate simultaneously within the other half‐cycle. The operation of the two content‐address ports is managed during the half‐cycle of the read phase. Thus, the three operations occur within a single cycle without latency. HSPICE simulations using 90 nm/1 V CMOS process reveal that the memory Alias Table provides the three operations within a one‐cycle of 1 GHz consuming an average power of 0.13 mW.

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Section: Write Circuit Architecture and Timingmentioning

confidence: 99%

Design of memory Alias Table based on the SRAM 8T‐Cell

Abdel‐hafeez

Otoom

Quwaider

2022

Circuit Theory & Apps

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“…Singh et al [105] have designed a data aware dynamic 9T SRAM cell to reduce the bitline power consumption. The dynamic nature of the cell flips the data faster at the bitline so that the average discharging activity is reduced.…”

Section: Data-aware Power-efficient Sram Cellmentioning

confidence: 99%

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

Singh¹

2017

Field - Programmable Gate Array

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The design of low-power SRAM cell becomes a necessity in today's FPGAs, because SRAM is a critical component in FPGA design and consumes a large fraction of the total power. The present chapter provides an overview of various factors responsible for power consumption in FPGA and discusses the design techniques of low-power SRAMbased FPGA at system level, device level, and architecture levels. Finally, the chapter proposes a data-aware dynamic SRAM cell to control the power consumption in the cell. Stack effect has been adopted in the design to reduce the leakage current. The various peripheral circuits like address decoder circuit, write/read enable circuits, and sense amplifier have been modified to implement a power-efficient SRAM-based FPGA.

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“…To improve the cell stability, a departure from the conventional 6‐T cells by increasing the transistor numbers has been suggested in the literature (see, e.g. ). The approach, however, increases the area of the cell and consequently the area of the memory part of the chip.…”

Section: Related Work: Conventional and Modified Structuresmentioning

confidence: 99%

A FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages

Ebrahimi

Asadpour

Afzali-Kusha

et al. 2015

Circuit Theory & Apps

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Summary In this paper, a SRAM cell structure which uses pMOS access transistors and predischarged bitlines is presented. By using the strained pMOS transistor technology, the degradation of the read static noise margin (SNM) at high supply voltages due to the aging, especially in the presence of symmetric stress, is suppressed. In contrast to conventional cell, the write margin of the proposed cell does not degrade considerably at low supply voltages. To assess the efficacy, the proposed cell is compared with conventional cell for two cases of unstrained and strained pMOS. A comparative study is performed using mixed mode device/circuit simulations for a gate length of 22 nm. The results show that the read SNM degradation due to the symmetric aging at the supply voltage of 1 V is about 6% after three years for the proposed strained structure, while degradations are 14%, 12%, and 11% for the unstrained proposed structure, unstrained, and strained conventional structures, respectively. In addition, the proposed cell has both read and write cell sigma yields higher than six for supply voltages ranging from 1 V down to 0.5 V while the other structures have read or write yields less than six at the minimum supply voltage. Through some work function tuning, the cell sigma yields of the other structures reach above six for both read and write while being still lower than those of the proposed structure. Copyright © 2015 John Wiley & Sons, Ltd.

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A data aware 9T static random access memory cell for low power consumption and improved stability

Cited by 8 publications

References 25 publications

Design of memory Alias Table based on the SRAM 8T‐Cell

Design of memory Alias Table based on the SRAM 8T‐Cell

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

A FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages

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