2015
DOI: 10.1002/cta.2057
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A FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages

Abstract: Summary In this paper, a SRAM cell structure which uses pMOS access transistors and predischarged bitlines is presented. By using the strained pMOS transistor technology, the degradation of the read static noise margin (SNM) at high supply voltages due to the aging, especially in the presence of symmetric stress, is suppressed. In contrast to conventional cell, the write margin of the proposed cell does not degrade considerably at low supply voltages. To assess the efficacy, the proposed cell is compared with … Show more

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Cited by 7 publications
(5 citation statements)
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“…Second, by allowing for per-block power gating, both power rails must be routed in the wordline direction. Unfortunately, this is not a common approach in industry, where a thin-cell SRAM cell is preferred for above-threshold operation (e.g., as seen by layouts in Sinangil et al [2011] and Ebrahimi et al [2015]). However, others have used wordline-oriented rails successfully in a variety of low-voltage design scenarios [Calhoun and Chandrakasan 2006;Verma and Chandrakasan 2008;Singh et al 2008;Cheng et al 2014;Chang et al 2015].…”
Section: Power Gating Of Faulty Blocksmentioning
confidence: 99%
“…Second, by allowing for per-block power gating, both power rails must be routed in the wordline direction. Unfortunately, this is not a common approach in industry, where a thin-cell SRAM cell is preferred for above-threshold operation (e.g., as seen by layouts in Sinangil et al [2011] and Ebrahimi et al [2015]). However, others have used wordline-oriented rails successfully in a variety of low-voltage design scenarios [Calhoun and Chandrakasan 2006;Verma and Chandrakasan 2008;Singh et al 2008;Cheng et al 2014;Chang et al 2015].…”
Section: Power Gating Of Faulty Blocksmentioning
confidence: 99%
“…The development of various circuits on a silicon chip at advanced CMOS technology nodes has elevated device reliability issues, which eventually degrades the circuit performance 22–26 . Device reliability issues like bias temperature instability (BTI) and hot carrier injection (HCI) are major concerns in integrated chips 27–29 . BTI and HCI lead to a shift in device parameters like the threshold voltage ( V TH ), drain current ( I D ), subthreshold slope ( SS ), transconductance ( g m ) 28 .…”
Section: Introductionmentioning
confidence: 99%
“…[22][23][24][25][26] Device reliability issues like bias temperature instability (BTI) and hot carrier injection (HCI) are major concerns in integrated chips. [27][28][29] BTI and HCI lead to a shift in device parameters like the threshold voltage (V TH ), drain current (I D ), subthreshold slope (SS), transconductance (g m ). 28 The major cause of BTI degradation is due to charge trapping in the oxide and at interface (substrate and gate oxide interface).…”
mentioning
confidence: 99%
“…Cache memories consume a significant portion of the power budget in the system‐on‐chip (SoC) applications. There are significant challenges for the complementary metal‐oxide‐semiconductor (CMOS)‐based design in sub‐22‐nm technologies 1 . As the channel length shrinks, short‐channel effects (SCEs) such as drain‐induced barrier lowering (DIBL) begin to manifest.…”
Section: Introductionmentioning
confidence: 99%