A DAQ Upgrade Solution for Belle II Experiment

Liu, Zhenan; Jia, Tao; Zhao, J.; Kou, Hanjun; Cao, P.; Song, Jiazheng; Gong, W. X.; Itoh, R.; Yamada, S.; Zhou, Q.

doi:10.1109/tns.2020.3006501

Cited by 3 publications

(1 citation statement)

References 8 publications

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“…ments [2][3][4] began to improve the bandwidth of DAQ by developing 10 Gbps ethernet 53 in FPGA. [5] implemented a 1G/10G ethernet hub firmware for processing multi-ports gigabit data and improving bandwidth.…”

Section: Jinst 16 P07044mentioning

confidence: 99%

A study of UDP and TCP FPGA implementation for data acquisition system

Zhang

Wang

et al. 2021

J. Inst.

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Two main protocol stacks for gigabit ethernet are currently widely adopted in the data acquisition system for high energy physics experiments. The first method is based on User Datagram Protocol (UDP), which transfer packets before an agreement is provided by the receiving party. However, the second method, called Transmission Control Protocol (TCP), establishes a connection through a process of the three-way handshake. We designed two FPGA projects, based on UDP and TCP respectively, on such a real application as ethernet communication module for ALICE calorimeters. The test of both projects is carried out on the same Xilinx Virtex-6 FPGA board, and data is captured through a professional network protocol analyzer. We analyzed the implementation methods and complexity, the variation patterns of data throughput, and the resource utilization of the two designs. The findings obtained under the same application scenario and test platform not only reveals the variation rule of actual data throughput, but also proved that the TCP would require twice as much FPGA resource for implementation as the UDP.

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Section: Jinst 16 P07044mentioning

confidence: 99%

A study of UDP and TCP FPGA implementation for data acquisition system

Zhang

Wang

et al. 2021

J. Inst.

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R &D of back-end electronics for improved resistive plate chambers for the phase 2 upgrade of the CMS end-cap muon system

Kou

Liu²,

Zhao³

et al. 2022

Radiat Detect Technol Methods

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The Large Hadron Collider (LHC) at European Organization for Nuclear Research is planned to be upgraded to the high luminosity LHC.Increasing the luminosity makes muon triggering reliable and offline reconstruction very challenging. To enhance the redundancy of the Compact Muon Solenoid (CMS) Muon system and resolve the ambiguity of track reconstruction in the forward region, an improved Resistive Plate Chamber (iRPC) with excellent time resolution will be installed in the Phase-2 CMS upgrade. The iRPC will be equipped with Front-End Electronics (FEE), which can perform high-precision time measurements of signals from both ends of the strip. New Back-End Electronics (BEE) need to be researched and developed to provide sophisticated functionalities such as interacting with FEE with shared links for fast, Slow Control (SC) and data, in addition to Trigger Primitives (TPs) generation and Data AcQuisition (DAQ).Method: The BEE prototype uses a homemade hardware board compatible with the MTCA standard, the Back-End Board (BEB). BEE interacts with FEE via a bidirectional 4.8 Gbps optical paired-link that integrates clock, data, and control information. The clock and fast/slow control commands

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The MicroTCA.4 Fast Control and Processing Board for Generic Control and Data Acquisition Applications in HEP Experiments

Zhang

et al. 2023

IEEE Trans. Nucl. Sci.

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A DAQ Upgrade Solution for Belle II Experiment

Cited by 3 publications

References 8 publications

A study of UDP and TCP FPGA implementation for data acquisition system

A study of UDP and TCP FPGA implementation for data acquisition system

R &D of back-end electronics for improved resistive plate chambers for the phase 2 upgrade of the CMS end-cap muon system

The MicroTCA.4 Fast Control and Processing Board for Generic Control and Data Acquisition Applications in HEP Experiments

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