The MicroTCA.4 Fast Control and Processing Board for Generic Control and Data Acquisition Applications in HEP Experiments

Self Cite

HYLITE (High dYnamic range free electron Laser Imaging deTEctor) is a charge-integration pixel readout chip designed for SHINE (Shanghai HIgh repetition rate XFEL aNd Extreme light facility). The target specifications for the full-size HYLITE chip include a pixel matrix of 128 × 128 pixels and a frame rate of 10 kHz. In order to meet these specifications, two small-scale chips, designated HYLITE0.1 and HYLITE0.2, were fabricated and underwent comprehensive testing. Some issues were discovered during tests including the noise performance and the error of output ADU (Analog Digital Units) codes. The HYLITE200S represents the third prototype chip developed to address the above issues. The CDS (Correlated Double Sampling) circuits and glitch-clear clock structures are integrated in pixels. Furthermore, to meet the data output rate requirements of the full-size chip, a high-speed data interface has been designed. Test results show that the signal-to-noise ratio is improved to 9.31 for a 12 keV single photon, and the ADU error is fixed. By integrating a phase-locked loop and a balanced encoding logic, the data interface can work steadily at a speed of 3.125 Gbps.

“…Chip test is carried out on a self-designed readout board [11]. The gains and ENC of different gain stages are listed in table 2.…”

Section: Characterizationmentioning

confidence: 99%

Optimized design and characterization of HYLITE, a charge-integration readout chip of XFEL

Li,

Wei,

Jiang

et al. 2024

Self Cite

“…The count value of the timer reflects the processing time of the entire hot-swap event from power-on request to completion. We use the MicroTCA.4 fast control and processing (u4FCP) board [11], an FPGA-based doublewidth MicroTCA.4-compatible AMC for generic control and data acquisition applications in HEP experiments. Two boards with different MCUs are inserted into the crate.…”

Section: Jinst 19 C04007 4 Real-time Performance Testingmentioning

confidence: 99%

Implementation and performance comparison of MMC firmware on RISC-V and ARM-based MCUs

Su,

Zhang,

Yang

2024

Self Cite

The control and data acquisition systems for high energy physics (HEP) applications require a suitable hardware platform to ensure system availability and reliability, so the micro telecommunications computing architecture (MicroTCA) standard is widely utilized in the field of HEP. As a fundamental component of the MicroTCA system, the advanced mezzanine card (AMC) requires efficient module management controller (MMC) to perform board monitoring and management. Therefore, the real-time responsiveness of the module management controller is crucial. Presently, most existing MMC solutions implemented on microcontroller chips with commercial architecture cores such as AVR and ARM. The open-source and customizable RISC-V instruction set architecture has gained widespread attention and adoption due to its advantages such as simplicity, modularity, scalability, low power consumption, and efficiency. In this study, we successfully implemented a MMC solution based on the RISC-V core microcontroller GD32VF103, and evaluated the real-time performance of MMC on both the GD32VF103 and the ARM-based STM32F100 through hot swap response time testing. The results reveal real-time performance of the firmware on the GD32VF103 chip compared to the STM32F100 chip, exhibiting a notable speed improvement of approximately 61.4%. Thus, RISC-V architecture chips exhibit significant potential as MMC solutions within MicroTCA systems.

“…final aggregation and output of data at a bandwidth of 200 Gbps. The AMC board is loaded with a high-performance Ultrascale + FPGA, featuring up to 2700 DSP48 units for carrying out convolution and image processing [6,7]. Considering that the 40 subunits have the same readout architecture, this paper will primarily focus on the architecture and performance of the subunit.…”

Section: Jinst 19 P06038mentioning

confidence: 99%

A study of the latest updates of the readout system for the hybird-pixel detector at HEPS

Li,

Zhang,

Wei

et al. 2024

Self Cite

The High Energy Photon Source (HEPS) represents a fourth-generation light source. This facility has made unprecedented advancements in accelerator technology, necessitating the development of new detectors to satisfy physical requirements such as single-photon resolution, large dynamic range, and high frame rates. Since 2016, the Institute of High Energy Physics has introduced the first user-experimental hybrid pixel detector, progressing to the fourth-generation million-pixel detector designed for challenging conditions, with the dual-threshold single-photon detector HEPS-Beijing PIXel (HEPS-BPIX) set as the next-generation target. HEPS-BPIX will employ the entirely new Application-Specific Integrated Circuit (ASIC) BP40 for pixel information readout. Data flow will be managed and controlled through readout electronics based on a two-tier Field-Programmable Gate Array (FPGA) system: the Front-End Electronics (FEE) and the Input-Output Board (IOB) handle the fan-out for 12 ASICs, and the μ4FCP is tasked with processing serial data on high-speed links, transferring pixel-level data to the back-end RTM and μTCA chassis, or independently outputting through a network port, enabling remote control of the entire detector. The new HEPS-BPIX firmware has undergone a comprehensive redesign and update to meet the electronic characteristics of the new chip and to improve the overall performance of the detector. We provide an overview of the core subunits of HEPS-BPIX, emphasizing the readout system, evaluating the new hardware and firmware, and highlighting some of its innovative features and characteristics.