2022
DOI: 10.1007/s41605-022-00340-6
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R &D of back-end electronics for improved resistive plate chambers for the phase 2 upgrade of the CMS end-cap muon system

Abstract: The Large Hadron Collider (LHC) at European Organization for Nuclear Research is planned to be upgraded to the high luminosity LHC.Increasing the luminosity makes muon triggering reliable and offline reconstruction very challenging. To enhance the redundancy of the Compact Muon Solenoid (CMS) Muon system and resolve the ambiguity of track reconstruction in the forward region, an improved Resistive Plate Chamber (iRPC) with excellent time resolution will be installed in the Phase-2 CMS upgrade. The iRPC will be… Show more

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Cited by 4 publications
(1 citation statement)
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“…The main task of the three FPGAs on the FEB is to time stamp the trigger signals received from the PETIROCs. The standard deviation of the Δ𝑇 (𝐿𝑅−𝐻 𝑅) is about 160 ps when measured with a proper time calibration after noise rejection, which corresponds to a spatial resolution of about 1.5 cm along the strip [6].…”
Section: The Irpc Chamber and The Readout Principlesmentioning
confidence: 99%
“…The main task of the three FPGAs on the FEB is to time stamp the trigger signals received from the PETIROCs. The standard deviation of the Δ𝑇 (𝐿𝑅−𝐻 𝑅) is about 160 ps when measured with a proper time calibration after noise rejection, which corresponds to a spatial resolution of about 1.5 cm along the strip [6].…”
Section: The Irpc Chamber and The Readout Principlesmentioning
confidence: 99%