A cycle-accurate compilation algorithm for custom pipelined datapaths

Abstract

Traditional high level synthesis (HLS) techniques generate a datapath and controller for a given behavioral description. The growing wiring cost and delay of today technologies require aggressive optimizations, such as interconnect pipelining, that cannot be done after generating the datapath and without invalidating the schedule. On the other hand, the increasing manufacturing complexities demand approaches that favor design for manufacturability (DFM).To address these problems we propose an approach in which the datapath of the architecture is fully allocated before scheduling and binding. We compile a C program directly to the datapath and generate the controller. We can support the entire ANSI C syntax because the datapath can be as complex as the datapath of a processor.Since there is no instruction abstraction in this architecture we call it No-Instruction-Set-Computer (NISC). As the first step towards realization of a NISC-based design flow, we present an algorithm that maps an application on a given datapath by performing scheduling and binding simultaneously. With this algorithm, we achieved up to 70% speedup on a NISC with a datapath similar to that of MIPS, compared to a MIPS gcc compiler. It also efficiently handles different datapath features such as pipelining, forwarding and multi-cycle units.

Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath

“…NISC [11] is a computer architecture which is composed of an arbitrary datapath and its controller. Different from the other computer architecture, NISC has no instruction set, and a set of control signals is directly stored in a control memory instead of a set of instructions.…”

Interrupt and Low-level Programming Support for Expanding the Application Domain of Statically-Scheduled Horizontal-Microcoded Architectures in Embedded Systems

“…CW and Status registers in Figure 1), the compiler should also make sure that the branch delay is considered correctly and is filled with other independent operations. Compilation algorithm detail is presented in [3] and [8]. Figure 2 shows the NISC flow of designing a custom architecture for a given application.…”

“…Based on this design approach, MIMOLA [1], TIPI [2], and NISC [3] use a statically-scheduled Horizontal Microcoded Architecture (HMA) style to maximize the explicit control of the programmer (or the compiler) over the datapath. In these approaches, the microcode is used to execute the program on the given datapath.…”

Automated Generation of Custom Processor Core from C Code

“…Furthermore, the controller generates a set of control signals that directly drives the data path, which allows for having any combination of control signals possible, not just the combinations that are allowed by instructions from a predefined IS. Moreover, it facilitates having compiler [3] that does not need to be modified every time that IS changes. Therefore, in this work, we adopt the methodology where the data path gets created separately from the controller.…”