Interrupt and Low-level Programming Support for Expanding the Application Domain of Statically-Scheduled Horizontal-Microcoded Architectures in Embedded Systems

Reshadi,; Gajski,

doi:10.1109/date.2007.364483

Cited by 5 publications

(3 citation statements)

References 12 publications

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“…Hierarchical modules have been described using netlist description using Generic Netlist Representation (GNR), which is a formal architecture description language (ADL) [17]. Pre-bound functions [18] have been used in order to achieve efficient utilization of resources and accurate execution timing. Different computational operations that can be executed in the same clock cycle have been merged to the same pre-bound function to maximize the exploitation of hardware resources and time.…”

Section: Results and Comparisonmentioning

confidence: 99%

NISC-Based Soft-Input–Soft-Output Demapper

Rizk

Baghdadi

Jézéquel

et al. 2015

IEEE Trans. Circuits Syst. II

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Applications in wireless digital communication field are becoming increasingly complex and diverse. Circuits and systems adopted in this application domain must not only consider performance and implementation constraints, but also the requirement of flexibility. The combination of flexibility and the ever increasing performance requirements demands design approach that provides better ways of controlling and managing hardware resources. Application Specific Instruction-set Processor (ASIP) design approach is key trend in designing flexible architectures. The ASIP concept implies dynamic scheduling of a set of instructions which generally leads to an overhead related to instruction decoding. No-Instruction-Set-Computer (NISC) concept has been introduced to reduce this overhead through the adoption of static scheduling. In this paper, the NISC approach is explored through a casestudy design of universal demapper for multiple wireless standards. The proposed design has common main architectural choices as a state-ofthe-art ASIP for comparison purpose. The obtained results illustrate a significant improvement in execution time and implementation area while using identical computational resources and supporting same flexibility parameters.

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Section: Results and Comparisonmentioning

confidence: 99%

NISC-Based Soft-Input–Soft-Output Demapper

Rizk

Baghdadi

Jézéquel

et al. 2015

IEEE Trans. Circuits Syst. II

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“…Also, automatic tools can be used to generate NISC architectures customized for one or more applications Gorjiara 2007;Trajkovic et al 2006]. NISC customization can be done in three ways: (1) by changing number and type of components and their interconnectivity; (2) by adding custom functional units (ranging from simple bitwise operations to complex multi-operand operations); [Reshadi et al 2008] (3) by adding one or more external accelerators [Reshadi and Gajski 2007;Reshadi 2007], which may be custom NISCs themselves. The difference between (2) and (3) is that in (2) compiler schedules the communication between the custom unit and the rest of the datapath, while in (3) the software should explicitly define the communication.…”

Section: Overview Of Nisc Technologymentioning

confidence: 99%

Merged Dictionary Code Compression for FPGA Implementation of Custom Microcoded PEs

Gorjiara

Reshadi

Gajski

2008

ACM Trans. Reconfigurable Technol. Syst.

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Horizontal Microcoded Architecture (HMA) is a paradigm for designing programmable highperformance processing elements (PEs). However, it suffers from large code size, which can be addressed by compression. In this article, we study the code size of one of the new HMA-based technologies called No-Instruction-Set Computer (NISC). We show that NISC code size can be several times larger than a typical RISC processor, and we propose several low-overhead dictionarybased code compression techniques to reduce its code size. Our compression algorithm leverages the knowledge of "don't care" values in the control words and can reduce the code size by 3.3 times, on average. Despite such good results, as shown in this article, these compression techniques lead to poor FPGA implementations because they require many on-chip RAMs. To address this issue, we introduce an FPGA-aware dictionary-based technique that uses the dual-port feature of on-chip RAMs to reduce the number of utilized block RAMs by half. Additionally, we propose cascading two-levels of dictionaries for code size and block RAM reduction of large programs. For an MP3 application, a merged, cascaded, three-dictionary implementation reduces the number of utilized block RAMs by 4.3 times (76%) compared to a NISC without compression. This corresponds to 20% additional savings over the best single level dictionary-based compression.

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“…In this context, the typical direct compilation of C codes describing the functionality using the NISC tool set gives inefficient hardware results. In order to achieve high performance and efficient resource utilization, the direct control of hardware resources is devised using pre-bound functions, which are C-like functions mapped by the compiler to specific hardware resources [22]. For a specific module, a pre-bound function is defined by declaring the proper control values and the utilized input/output ports.…”

Section: Adopted Design Flowmentioning

confidence: 99%

Design and Prototyping Flow of Flexible and Efficient NISC-Based Architectures for MIMO Turbo Equalization and Demapping

et al. 2016

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In the domain of digital wireless communication, flexible design implementations are increasingly explored for different applications in order to cope with diverse system configurations imposed by the emerging wireless communication standards. In fact, shrinking the design time to meet market pressure, on the one hand, and adding the emerging flexibility requirement and, hence, increasing system complexity, on the other hand, require a productive design approach that also ensures final design quality. The no instruction set computer (NISC) approach fulfills these design requirements by eliminating the instruction set overhead. The approach offers static scheduling of the datapath, automated register transfer language (RTL)synthesis and allows the designer to have direct control of hardware resources. This paper presents a complete NISC-based design and prototype flow, from architecture specification till FPGA implementation. The proposed design and prototype flow is illustrated through two case studies of flexible implementations, which are dedicated to low-complexity MIMO turbo-equalizer and a universal turbo-demapper. Moreover, the flexibility of the proposed prototypes allows supporting all communication modes defined in the emerging wireless communication standards, such LTE, LTE-Advanced, WiMAX, WiFi and DVB-RCS. For each prototype, its functionality is evaluated, and the resultant performance is verified for all system configurations.

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Interrupt and Low-level Programming Support for Expanding the Application Domain of Statically-Scheduled Horizontal-Microcoded Architectures in Embedded Systems

Abstract: The

Cited by 5 publications

References 12 publications

NISC-Based Soft-Input–Soft-Output Demapper

NISC-Based Soft-Input–Soft-Output Demapper

Merged Dictionary Code Compression for FPGA Implementation of Custom Microcoded PEs

Design and Prototyping Flow of Flexible and Efficient NISC-Based Architectures for MIMO Turbo Equalization and Demapping

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