A Cost-efficient Input Vector Monitoring Concurrent On-line BIST Scheme Based on Multilevel Decoding Logic

Wu, Tiebin; Liu, Hengzhu; Liu, Peng-Xia; Guo, Dong‐Sheng; Sun, Haiming

doi:10.1007/s10836-013-5380-1

Cited by 5 publications

(2 citation statements)

References 17 publications

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“…19,20 Referring to Ref. 6, in this paper we characterize the input environment in terms of input signal probabilities and model an SEU upset as a single event upset (SET) on a given combinational circuit to design the STMR system.…”

Section: Output Signal Probabilities Computation Of a Boolean Gatementioning

confidence: 99%

Multi-objective evolutionary design of selective triple modular redundancy systems against SEUs

Yao

Chen

et al. 2015

Chinese Journal of Aeronautics

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To improve the reliability of spaceborne electronic systems, a fault-tolerant strategy of selective triple modular redundancy (STMR) based on multi-objective optimization and evolvable hardware (EHW) against single-event upsets (SEUs) for circuits implemented on field programmable gate arrays (FPGAs) based on static random access memory (SRAM) is presented in this paper. Various topologies of circuit with the same functionality are evolved using EHW firstly. Then the SEU-sensitive gates of each circuit are identified using signal probabilities of all the lines in it, and each circuit is hardened against SEUs by selectively applying triple modular redundancy (TMR) to these SEU-sensitive gates. Afterward, each circuit hardened has been evaluated by SEU Simulation, and the multi-objective optimization technology is introduced to optimize the area overhead and the number of functional errors of all the circuits. The proposed fault-tolerant strategy is tested on four circuits from microelectronics center of North Carolina (MCNC) benchmark suite. The experimental results show that it can generate innovative trade-off solutions to compromise between hardware resource consumption and system reliability. The maximum savings in the area overhead of the STMR circuit over the full TMR design is 58% with the same SEU immunity.

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Section: Output Signal Probabilities Computation Of a Boolean Gatementioning

confidence: 99%

Multi-objective evolutionary design of selective triple modular redundancy systems against SEUs

Yao

Chen

et al. 2015

Chinese Journal of Aeronautics

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“…Paper [12] Proposes a input vector monitoring scheme for concurrent BIST for on-line testing. To reduce hardware cost of paper [12], a new Multilevel Decoding Logic is proposed in paper [13]. Paper [14] presents a novel BIST architecture for comute the number of switch of the circuits to reduce the test power.…”

Section: Introductionmentioning

confidence: 99%

A new BIST scheme with encoding logic to achieve complete fault coverage

Zhang

Mei

Wang

et al. 2015

Future Energy, Environment and Materials II

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Abstract-Built-in Self Test(BIST)has been proved as one of the effective design for testability techniques, where on-chip test architectures are designed to test the digital circuits themselves. To reduce test application time and improve fault coverage, A deterministic Built-in Self Test(BIST) technique that can get complete fault coverage without using any storage device is proposed in this paper. The test architecture contains a novel on chip encoding logic that generates all required test vectors in real time. Experimental results show that the proposed technique requires much less test application time to achieve complete fault coverage for all testable stuck-at faults with reasonable hardware cost.

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A Low-cost BIST Design Supporting Offline and Online Tests

Menbari

Jahanirad

2022

J Electron Test

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A Cost-efficient Input Vector Monitoring Concurrent On-line BIST Scheme Based on Multilevel Decoding Logic

Cited by 5 publications

References 17 publications

Multi-objective evolutionary design of selective triple modular redundancy systems against SEUs

Multi-objective evolutionary design of selective triple modular redundancy systems against SEUs

A new BIST scheme with encoding logic to achieve complete fault coverage

A Low-cost BIST Design Supporting Offline and Online Tests

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