A concurrent testing technique for digital circuits

Saluja, Kewal K.; Sharma, Rupendra Kumar; Kime, C.R.

doi:10.1109/43.16803

Cited by 68 publications

(22 citation statements)

References 6 publications

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“…The initial work on vector monitoring concurrent BIST (C-BIST) was reported by Saluja [7]. The test generator of C-BIST is a linear feedback shift register (LFSR) and the active test set consists of exactly one active test vector i.e.…”

Section: Area Overhead (Ao)mentioning

confidence: 99%

Online Fault Detection, Diagnosis and Repair using RA

2015

IJSR

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Built-in self-test (BIST) is a commonly used design technique that allows a circuit to test circuit itself. But for this circuit have to switch in off-line mode which unnecessary waste time and power to avoid this best method is online bist In this paper BIST architecture is implemented for Detection, Diagnosis and Repair of various faulty circuits. A complete and versatile online test solution based on reconfigurable test architecture is presented in this paper. Reconfigurable test architecture works alongside the controllers for online concurrent fault detection. The output vectors of the controllers are concurrently monitored and any fault present is detected in a few cycles from the sensitization of the fault. The architecture is then reprogrammed to a similar set of diagnostic hardware to locate a sub block which is the cause for the fault. The same architecture is then reprogrammed to replace the faulty block thereby completing repair. The test architecture is designed based on configurable logic blocks. The design has several advantages viz. (i) it works well for critical VLSI controllers where shutting down or suspending the operation of a controller for testing is not possible and where the fault needs to be detected at the earliest, during the run time of the system, (ii) after a fault is detected, diagnosis can be performed online, (iii) once a faulty block is located, repair is also done online. Since fault detection, diagnosis and repair are completed online with one test hardware, the effective hardware overhead is negligible and the system can resume its function within a brief period. The applicability of the architecture is demonstrated for the control blocks in OC8051.

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Section: Area Overhead (Ao)mentioning

confidence: 99%

Online Fault Detection, Diagnosis and Repair using RA

2015

IJSR

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“…Since the complete memory is scanned during a periodic refresh operation, this phase naturally offers itself for concurrently computing a test characteristic g i as proposed above [12]. In contrast to more general schemes for the concurrent testing of digital circuits, it is guaranteed that all necessary test inputs actually appear during a test phase [24]. However, in contrast to an offline BIST implementation, it must be guaranteed that the computation can be completed within the time slot available for the periodic refresh operation.…”

Section: Introductionmentioning

confidence: 99%

Efficient online and offline testing of embedded DRAMs

Hellebrand

Wunderlich

Ivaniuk

et al. 2002

IEEE Trans. Comput.

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AbstractÐThis paper presents an integrated approach for both built-in online and offline testing of embedded DRAMs. It is based on a new technique for output data compression which offers the same benefits as signature analysis during offline test, but also supports efficient online consistency checking. The initial fault-free memory contents are compressed to a reference characteristic and compared to test characteristics periodically. The reference characteristic depends on the memory contents, but unlike similar characteristics based on signature analysis, it can be easily updated concurrently with WRITE operations. This way, changes in memory do not require a time consuming recomputation. The respective test characteristics can be efficiently computed during the periodic refresh operations of the dynamic RAM. Experiments show that the proposed technique significantly reduces the time between the occurrence of an error and its detection (error detection latency). Compared to error detecting codes (EDC) it also achieves a significantly higher error coverage at lower hardware costs. Therefore, it perfectly complements standard online checking approaches relying on EDC, where the concurrent detection of certain types of errors is guaranteed, but only during READ operations accessing the erroneous data.

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“…In an effort to explore the solution space, we observe that for every input combination, each output bit has the ability to detect a subset of all faults in the circuit, as shown in Figure (2). Guaranteeing detection of all non-redundant faults requires that the prediction logic be capable of generating an adequate set of output bits, such that the union of detected Figure 2.…”

Section: Reduced Observation Width Replicationmentioning

confidence: 99%

“…Similarly to [2,3,11], we assume a uniform distribution at the circuit inputs and employ fault simulation of randomly generated input sequences. More specifically, for each method we use HOPE [15] to perform two fault simulations of the same sequence of randomly generated inputs, once observing both the test output and the circuit outputs, and a second time observing only the test output.…”

Section: Fault Detection Latencymentioning

confidence: 99%