A Complementary Metal–Oxide–Semiconductor Image Sensor with 2.0 e<sup>-</sup> Random Noise and 110 ke<sup>-</sup> Full Well Capacity and Noise Measurement of Pixel Transistors Using Column Source Follower Readout Circuits

Kohara, Takahiro; Lee, Woonghee; Mizobuchi, Koichi; Sugawa, Shigetoshi

doi:10.1143/jjap.49.04de02

Cited by 3 publications

(2 citation statements)

References 9 publications

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“…Since floating capacitor load readout operation reduces the peripheral circuits, the area of pixel array occupies almost all chip area. This chip uses shared pixel technique [14][15][16] and column SF for high column readout gain [17] . The chip size is 3.4mm H × 2.5mm V , the pixel size is 2.8µm H × 2.8µm V , and the number of pixel is 1140 H × 768 V .…”

Section: Measurement Results Of Fabricated Chipmentioning

confidence: 99%

Analysis of pixel gain and linearity of CMOS image sensor using floating capacitor load readout operation

et al. 2015

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In this paper, we demonstrate that the floating capacitor load readout operation has higher readout gain and wider linearity range than conventional pixel readout operation, and report the reason. The pixel signal readout gain is determined by the transconductance, the backgate transconductance and the output resistance of the in-pixel driver transistor and the load resistance. In floating capacitor load readout operation, since there is no current source and the load is the sample/hold capacitor only, the load resistance approaches infinity. Therefore readout gain is larger than that of conventional readout operation. And in floating capacitor load readout operation, there is no current source and the amount of voltage drop is smaller than that of conventional readout operation. Therefore the linearity range is enlarged for both high and low voltage limits in comparison to the conventional readout operation. The effect of linearity range enlargement becomes more advantageous when decreasing the power supply voltage for the lower power consumption. To confirm these effects, we fabricated a prototype chip using 0.18um 1-Poly 3-Metal CMOS process technology with pinned PD. As a result, we confirmed that floating capacitor load readout operation increases both readout gain and linearity range.

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Section: Measurement Results Of Fabricated Chipmentioning

confidence: 99%

Analysis of pixel gain and linearity of CMOS image sensor using floating capacitor load readout operation

et al. 2015

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“…As a comparison, we have produced the image sensor using surface channel MOSFETs for in-pixel driver transistors. In addition, this CMOS image sensor uses column SF which improves readout gain by increasing chip height of only some pixels [5] . Using the floating capacitor load readout operation, this image sensor has removed constant current sources and analog memories which are necessary in conventional readout operation.…”

Section: Resultsmentioning

confidence: 99%

A CMOS image sensor using floating capacitor load readout operation

et al. 2013

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In this paper, a CMOS image sensor using floating capacitor load readout operation has been discussed. The floating capacitor load readout operation is used during pixel signals readout. And this operation has two features: 1. in-pixel driver transistor drives load capacitor without current sources, 2. parasitic capacitor of pixel output vertical signal line is used as a sample/hold capacitor. This operation produces three advantages: a smaller chip size, a lower power consumption, and a lower output noise than conventional CMOS image sensors. The prototype CMOS image sensor has been produced using 0.18 m 1-Poly 3-Metal CMOS process technology with pinned photodiodes. The chip size is 2.5 mm H  2.5 mm V , the pixel size is 4.5 m H  4.5 m V , and the number of pixels is 400 H  300 V . This image sensor consists of only a pixel array, vertical and horizontal shift registers, column source followers of which height is as low as that of some pixels and output buffers. The size of peripheral circuit is reduced by 90.2 % of a conventional CMOS image sensor. The power consumption in pixel array is reduced by 96.9 %. Even if the power consumption of column source follower is included, it reduced by 39.0 %. With an introduction of buried channel transistors as in-pixel driver transistors, the dark random noise of pixels of the floating capacitor load readout operation CMOS image sensor is 168 V rms . The noise of conventional image sensor is 466 V rms ; therefore, reduction of 63.8 % of noise was achieved.

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[Paper] Floating Capacitor Load Readout Operation for Small, Low Power Consumption and High S/N Ratio CMOS Image Sensors

Wakashima

Kusuhara

Kuroda

et al. 2016

MTA

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Floating capacitor load readout operation for small, low power consumption and high S/N ratio CMOS image sensors and its effects are demonstrated. This readout operation utilizes a floating capacitor load instead of a constant current load as pixel SF driver, and the parasitic capacitor of pixel output vertical signal line as column sample/hold capacitor. Using a 0.18 µm CMOS image sensor technology, two CMOS image sensors were fabricated to verify the effects. The ratio of pixel area to the total effective area is over 92 %. The power consumption for pixel signal readout and pixel readout noise were decreased by over 97 % and 63.8 %, respectively. Also a higher readout gain and a wider linear response range were obtained. Furthermore, it was confirmed that this readout operation becomes more advantageous when decreasing the power supply voltage, which is favorable for ultra-low power sensor network system applications.

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A Complementary Metal–Oxide–Semiconductor Image Sensor with 2.0 e^- Random Noise and 110 ke^- Full Well Capacity and Noise Measurement of Pixel Transistors Using Column Source Follower Readout Circuits

Cited by 3 publications

References 9 publications

Analysis of pixel gain and linearity of CMOS image sensor using floating capacitor load readout operation

Analysis of pixel gain and linearity of CMOS image sensor using floating capacitor load readout operation

A CMOS image sensor using floating capacitor load readout operation

[Paper] Floating Capacitor Load Readout Operation for Small, Low Power Consumption and High S/N Ratio CMOS Image Sensors

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A Complementary Metal–Oxide–Semiconductor Image Sensor with 2.0 e- Random Noise and 110 ke- Full Well Capacity and Noise Measurement of Pixel Transistors Using Column Source Follower Readout Circuits

Cited by 3 publications

References 9 publications

Analysis of pixel gain and linearity of CMOS image sensor using floating capacitor load readout operation

Analysis of pixel gain and linearity of CMOS image sensor using floating capacitor load readout operation

A CMOS image sensor using floating capacitor load readout operation

[Paper] Floating Capacitor Load Readout Operation for Small, Low Power Consumption and High S/N Ratio CMOS Image Sensors

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A Complementary Metal–Oxide–Semiconductor Image Sensor with 2.0 e^- Random Noise and 110 ke^- Full Well Capacity and Noise Measurement of Pixel Transistors Using Column Source Follower Readout Circuits