A comparison of large I/O flip chip and wire bonded packages

Bulumulla, S.B.; Caggiano, M.F.; Lischner, D. J.; Wolf, R.K.

doi:10.1109/ectc.2001.927965

Cited by 4 publications

(2 citation statements)

References 4 publications

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“…[1] Though wirebond packaging has been widely used in previous technologies for low cost markets, current analyses of applications in the 1-10 Gbps range is limited. Whereas wirebond packages are generally believed to have very poor high frequency behavior [2], the performance has not been well quantified. As recent developments reported in industry products, wirebond packages are finding greater potential in high speed applications than previously expected, as demonstrated in [3].…”

Section: Introductionmentioning

confidence: 99%

Competitiveness and Technical Challenges of Low Cost Wirebond Packaging for High Speed SerDes Applications in ASICs

Zwitter¹,

Na²,

Arseneault³

et al. 2007

2007 Proceedings 57th Electronic Components and Technology Conference

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This paper discusses the challenges in balancing the wireability, performance, and cost of low cost wirebond packaging for high speed SerDes applications in application specific integrated circuits (ASICs). In-depth analysis was performed using 3D electromagnetic simulation to evaluate the effect on performance of various design factors along the signal path of the wirebond package, including bondwire, microstrip, and ball grid array (BGA) assignment. The tradeoff between wireability and performance of these design factors is discussed. Hardware measurements were performed on a functioning high speed SerDes test site which was designed to optimize wireability for the application while still achieving performance well beyond the 3 gigabits per second (Gbps) data rate for which it was designed. Projections are made concerning design variables that can be adjusted to meet the requirements of wire count, package size, and performance, enabling the ability to design for a broad application space in high speed SerDes applications.

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Section: Introductionmentioning

confidence: 99%

Competitiveness and Technical Challenges of Low Cost Wirebond Packaging for High Speed SerDes Applications in ASICs

Zwitter¹,

Na²,

Arseneault³

et al. 2007

2007 Proceedings 57th Electronic Components and Technology Conference

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show abstract

“…A high I/O count is required for most of the high‐speed ASICs (Bulumulla, 2001) but the traditional packages techniques such as plastic leaded chip carrier (IBM, 1986), thin small outline package (Lau et al , 1993) and the quad flat packs (QFP) (Guenin, 1994) are difficult in fulfilling the requirement. Alternatively, the area‐array solder‐bumped flip‐chip technology (Lau, 1995) is a positive move to resolve this problem.…”

Section: Introductionmentioning

confidence: 99%

In‐house development of low cost automatic IC workcell for BGA solder ball attachment

Tam¹,

Chan

et al. 2008

Assembly Automation

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PurposeThe purpose of this paper is to develop a cost effective ball grid array (BGA) workcell for solder ball attachment.Design/methodology/approachThis paper presents the construction of a low‐cost high‐efficiency automatic ball attachment workcell. In fact, it is an economical means of simultaneous placement of all solder balls on BGA substrates containing multiple BGA units as well as singulated substrates. Common industry problems such as the effect of static charges, the solder ball oxidation, the missing ball, the extra ball, the ball alignment, the deformed ball and, etc. will be addressed and critical issues affecting yield will also be discussed in this paper.FindingsBGA is a popular integrated circuit packaging that is often applied in laptop computers and other handheld electronic devices for the provision of a high‐connection count in a relatively small area. However, the cost of a market available BGA solder ball attachment workcell is very expensive and the flexibility in fitting various customized process is usually low.Originality/valueThe developed workcell cost is about half of the market available machines with similar specifications; the yield achieved is within three sigma confidence interval with competitive output rate. The maintenance and troubleshooting are easy since the machine was developed by the in‐house engineering team.

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High speed electrical performance comparison between bump with RDL and wire bond technologies

Chiu

Hung

Proceedings of the 4th International Symposium on Electronic Materials and Packaging, 2002.

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As the chip clock rate keeps increasing, the electrical performance of wire bond and bump connection which are using in advance package is becoming the important consideration while choosing the package solution for the high-speed devices. In this paper, the electrical perfo%ance of the wire bond technology and bump with RDL technology has been presented. By using the full-wave 3D electromagnetic simulators, the experimental results including the passive parasitic parameter analysis (AC Resistance, Inductance and Capacitance) and scattering parameter analysis will be pnented. Discussions on the rise time, cross talk noise, propagation delay for the IOGbitk signal are also included.

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A comparison of large I/O flip chip and wire bonded packages

Cited by 4 publications

References 4 publications

Competitiveness and Technical Challenges of Low Cost Wirebond Packaging for High Speed SerDes Applications in ASICs

Competitiveness and Technical Challenges of Low Cost Wirebond Packaging for High Speed SerDes Applications in ASICs

In‐house development of low cost automatic IC workcell for BGA solder ball attachment

High speed electrical performance comparison between bump with RDL and wire bond technologies

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