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This paper discusses the challenges in balancing the wireability, performance, and cost of low cost wirebond packaging for high speed SerDes applications in application specific integrated circuits (ASICs). In-depth analysis was performed using 3D electromagnetic simulation to evaluate the effect on performance of various design factors along the signal path of the wirebond package, including bondwire, microstrip, and ball grid array (BGA) assignment. The tradeoff between wireability and performance of these design factors is discussed. Hardware measurements were performed on a functioning high speed SerDes test site which was designed to optimize wireability for the application while still achieving performance well beyond the 3 gigabits per second (Gbps) data rate for which it was designed. Projections are made concerning design variables that can be adjusted to meet the requirements of wire count, package size, and performance, enabling the ability to design for a broad application space in high speed SerDes applications.

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This paper discusses a package design technique to enhance high speed signal performance by reducing the large discontinuity effects at the vias and solder ball interfaces. In the technique, an intentional counter-discontinuity in complementary phase to existing discontinuity is inserted to mitigate the existing discontinuity. Transmission line behavior of short multiple discontinuities are analyzed using theoretical approximation and simulation examples to demonstrate the validity of the technique. The techniques are then applied to package via and solder ball transitions of high speed differential nets using 3D simulation to evaluate improvement at target frequencies versus impact in bandwidth. IntroductionDiscontinuities in high speed package interconnects are having more significant impacts as data rates have increased to 1OGbps and higher. Vias in thick laminates cores and solder balls at the package to PCB interface introduce large capacitive discontinuities, while bond wires in wirebond packages introduce a large inductive discontinuity. In these cases, the behavior of the structure is inherent to the package and the designer has limited options to control the impedance. As an effort to decrease capacitive discontinuity in solder ball path, intentional voids in ground conductor layers above the solder balls of high speed signal nets have been used in recent package design practice.[1] While voiding the ground conductor helps reduce capacitance and discontinuity to a degree, it can interfere with neighboring signal structures. This paper looks into different approaches for further improvement. The technique uses transmission line behavior in short discontinuities. For example, if the existing discontinuity is capacitive, an inductive discontinuity is introduced to compensate for the capacitive discontinuity to achieve matching impedance as seen by the traveling wave over a short distance. This inductance technique has been used in chip termination of high speed circuits and ESD devices to compensate for the large parasitic capacitance of chip circuits and pads. [2] [3] In the next sections, transmission line behavior with short discontinuities is revisited from distributed line behavior and lumped element circuit point of views. Package design structures in via-solder ball transition are studied for discontinuity compensation and its effectiveness is discussed using 3D EM (electromagnetic) simulations.

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