This paper discusses the challenges in balancing the wireability, performance, and cost of low cost wirebond packaging for high speed SerDes applications in application specific integrated circuits (ASICs). In-depth analysis was performed using 3D electromagnetic simulation to evaluate the effect on performance of various design factors along the signal path of the wirebond package, including bondwire, microstrip, and ball grid array (BGA) assignment. The tradeoff between wireability and performance of these design factors is discussed. Hardware measurements were performed on a functioning high speed SerDes test site which was designed to optimize wireability for the application while still achieving performance well beyond the 3 gigabits per second (Gbps) data rate for which it was designed. Projections are made concerning design variables that can be adjusted to meet the requirements of wire count, package size, and performance, enabling the ability to design for a broad application space in high speed SerDes applications.
Maskless patterning of Mo and Si was done by implanting 50 keV focused Ga+ ion beam and by plasma etching using CF4 gas. The implantation is done to modify the chemical properties of the sample surface. It was found that Mo films became etch-resistant for the plasma etching after implantation at a dose higher than 4×1015 /cm2. Si crystals showed a positive tone pattern due to a radiation enhanced etching at a dose lower than 5x1016/cm2. At higher doses, the etching rate decreased and above 8 x 1016/cm2, no etching was observed in the implanted region. Patterns with a thickness of a several hundred nanometers were formed by the present maskless patterning technique.
Laminate type FBGA package is one of the advanced solutions of economic chip scale package, effective for applications that require low profile and small area as cellular phones or hand held products. IBM stared to use an advanced package, DCS ( Dual Chip Stacked ) -FBGA, to obtain higher communication rate between dual semiconductor chips into one package, which were originally placed on different packages on wider space cards.During the development stage two subjects were concemed as, damage on the bottom-chip circuits under the top-chip placement region, and the reliability impacts. The top and bottom chip size combination in DCS-FBGA has a large difference ratio comparing to memory chips stack type packages, which is applied widly in the industry. Assessment studies on different CTE materials, chip thickness, construction, attachment methods, and reliability performances were analyzed. The result was validated by experiments to monitor the contact resistance discrepancy on the chip. To minimize these impacts, we confirmed the correlation between chip attach technique and mechanical reliability.This paper contains details of the phenomenon, solutions and effectiveness.
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