A comparison of five different multiprocessor SoC bus architectures

Ryu, Kyeong Keol; Shin, Eung S.; Mooney, Vincent J.

doi:10.1109/dsd.2001.952283

Cited by 41 publications

(6 citation statements)

References 6 publications

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“…So it will be used here, too. Our system design was taking into account related work like bus architectures in [23], and another multiprocessor architecture with NIOS II softcores [18].…”

Section: Overviewmentioning

confidence: 99%

Efficient Traffic Simulation Using Agents within the Global Cellular Automata Model

Schäck

Hoffmann

Heenes

2011

IJNC

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We present a mapping of the well known Nagel-Schreckenberg algorithm for traffic simulation onto the Global Cellular Automata (GCA) model using agents. The GCA model consists of a collection of cells which change their states synchronously depending on the states of their neighbors like in the classical CA (Cellular Automata) model. In contrast to the CA model the neighbors can be freely and dynamically selected at runtime. The vehicles are considered as agents that are modeled as GCA cells. An agent is linked to its agent in front, and an empty cell is linked to its agent behind. In the current generation t the position of an agent is already computed for the generation t+2. Thereby the agents movements and all cell updates can directly be calculated as defined by the cell rule. No searching of specific cells during the computation is necessary. Compared to an optimized CA algorithm (with searching for agents) the GCA algorithm executes significantly faster, especially for low traffic densities and high vehicle speeds. Simulating one lane with a density of 10% on an FPGA multiprocessor system resulted in a speed-up (measured in clock ticks) of 14.75 for a system with 16 NIOS II processors.

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“…So it will be used here, too. Our system design was taking into account related work like bus architectures in [23], and another multiprocessor architecture with NIOS II softcores [18].…”

Section: Overviewmentioning

confidence: 99%

Efficient Traffic Simulation Using Agents within the Global Cellular Automata Model

Schäck

Hoffmann

Heenes

2011

IJNC

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“…We demonstrate how our MPSoC platform enables the exploration of different hardware architectures and the analysis of complex interaction patterns between parallel processors sharing storage and communication resources. In particular we demonstrate the impact of various bus arbitration policies on system performance, one of the most critical elements in MPSoC design, as demonstrated in previous work [12][13][14][15].…”

Section: Introductionmentioning

confidence: 97%

MPARM: Exploring the Multi-Processor SoC Design Space with SystemC

Benini

Bertozzi

Bogliolo

et al. 2005

J VLSI Sign Process Syst Sign Image Video Technol

206

100

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Technology is making the integration of a large number of processors on the same silicon die technically feasible. These multi-processor systems-on-chip (MP-SoC) can provide a high degree of flexibility and represent the most efficient architectural solution for supporting multimedia applications, characterized by the request for highly parallel computation. As a consequence, tools for the simulation of these systems are needed for the design stage, with the distinctive requirement of simulation speed, accuracy and capability to support design space exploration. We developed a complete simulation platform for a MP-SoC called MP-ARM, based on SystemC as modelling and simulation environment, and including models for processors, the AMBA bus compliant communication architecture, memory models and support for parallel programming. A fully operating linux version for embedded systems has been ported on this platform, and a cross-toolchain has been developed as well. Our MP simulation environment turns out to be a powerful tool for the MP-SOC design stage. As an example thereof, we use our tool to evaluate the impact on system performance of architectural parameters and of bus arbitration policies, showing that the effectiveness of a particular system configuration strongly depends on the application domain and the generated traffic profile

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“…Since the scheduling strategy is directly related with the OCB system, an appropriate OCB architecture and arbitration mechanism should be well designed. Normally, there are two principles for OCB design [2]: 1) ensures that the real-time performance of the system should be achieved; 2) allocates bus bandwidth to each task effectively, minimizes the size of on-chip buffers.…”

Section: Introductionmentioning

confidence: 99%

On-Chip Bus Design for HDTV SoC Decoder

2010

2010 6th International Conference on Wireless Communications Networking and Mobile Computing (WiCOM)

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it is a great challenge to design an On-Chip Bus (OCB) system to meet the extremely high bandwidth requirements in HDTV SoC decoder. In this paper, an OCB system with high throughput and flexibility based on the multibus architecture is proposed. A bus switch with multi-level arbiter structure is also constructed thereafter. Simulation results show that the OCB system can ensure the real-time performance of the whole decoder very well.

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A comparison of five different multiprocessor SoC bus architectures

Cited by 41 publications

References 6 publications

Efficient Traffic Simulation Using Agents within the Global Cellular Automata Model

Efficient Traffic Simulation Using Agents within the Global Cellular Automata Model

MPARM: Exploring the Multi-Processor SoC Design Space with SystemC

On-Chip Bus Design for HDTV SoC Decoder

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