MPARM: Exploring the Multi-Processor SoC Design Space with SystemC

Benini, Luca; Bertozzi, Davide; Bogliolo, Alessandro; Menichelli, Francesco; Olivieri, Mauro

doi:10.1007/s11265-005-6648-1

Cited by 206 publications

(104 citation statements)

References 12 publications

(10 reference statements)

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“…We use accurate statistics generated from an H.264 decoder that we have parallelized and executed on a sophisticated multiprocessor virtual platform simulator. In fact, in this work, we use the multiprocessor ARM (MPARM) virtual platform simulator [5], which is a complete SystemC simulation environment for MPSoC architectural design and exploration. MPARM provides cycle-accurate and bus signalaccurate simulation for different processors.…”

Section: B H264 Decoder -Energy Deadline Miss Rates and Overheadmentioning

confidence: 99%

A unified online directed acyclic graph flow manager for multicore schedulers

Kanoun

Atienza

Mastronarde³

et al. 2014

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Abstract-Numerous Directed-Acyclic Graph (DAG) schedulers have been developed to improve the energy efficiency of various multi-core systems. However, the DAG monitoring modules proposed by these schedulers make a priori assumptions about the workload and relationship between the task dependencies. Thus, schedulers are limited to work on a limited subset of DAG models. To address this problem, we propose a unified online DAG monitoring solution independent from the connected scheduler and able to handle all possible DAG models. Our novel low-complexity solution processes online the DAG of the application and provides relevant information about each task that can be used by any scheduler connected to it. Using H.264/AVC video decoding as an illustrative application and multiple configurations of complex synthetic DAGs, we demonstrate that our solution connected to an external simple energy-efficient scheduler is able to achieve significant improvements in energy-efficiency and deadline miss rates compared to existing approaches.

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Section: B H264 Decoder -Energy Deadline Miss Rates and Overheadmentioning

confidence: 99%

A unified online directed acyclic graph flow manager for multicore schedulers

Kanoun

Atienza

Mastronarde³

et al. 2014

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

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“…COTSon runs an operating system and applications on top of it. The MPARM SystemC framework [22] is a complete system-level simulator, and includes cycle-accurate cores, complex memory hierarchies and bus-based interconnection mechanisms. A linux port for MPARM is underway.…”

Section: Related Workmentioning

confidence: 99%

Fast and cycle-accurate modeling of a multicore processor

Khan

Vijayaraghavan

Boyd-Wickizer

et al. 2012

2012 IEEE International Symposium on Performance Analysis of Systems &Amp; Software

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Abstract-An ideal simulator allows an architect to swiftly explore design alternatives and accurately determine their impact on performance. Design exploration requires simulators to be easily modifiable, and accurate performance estimates require detailed models. Unfortunately, detailed modeling not only impacts the ease with which a simulator can be modified, but also the speed at which it can be executed, resulting in fidelity being traded for simulation speed. Although FPGA-based simulators have dramatically higher speed than software simulators, sacrificing fidelity is still common.In this paper we present Arete, an FPGA-based processor simulator, which offers high performance along with accuracy and modifiability. We begin with a cycle-level specification of a multicore architecture which includes realistic in-order cores and detailed models of shared, coherent memory and on-chip network. We then describe how this specification is implemented faithfully and efficiently on FPGAs. Arete delivers a performance of up to 11 MIPS per core. We run a subset of the PARSEC benchmark suite on top of off-the-shelf SMP Linux, and achieve an average performance of 55 MIPS for an 8-core model. We also describe two significant architectural explorations: one involving three different branch predictors and the other requiring major modifications to the cache-coherence protocol.

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“…However, we only forward the control tokens if there is a chance of deadlock in simulation. MPARM [10] is an environment for MPSoC design space exploration using SystemC. It is complete platform solution for MPSoC simulation composed of processor models (ARM) bus models (AMBA), memory models, hardware support for SMP (hardware semaphores), and a software development toolset including a C compiler and an operating system.…”

Section: Related Workmentioning

confidence: 99%

Performance evaluation of concurrently executing parallel applications on multi-processor systems

Shabbir

Kumar

Mesman

et al. 2009

2009 International Symposium on Systems, Architectures, Modeling, and Simulation

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Abstract-Multi-processors are increasingly being used in modern embedded systems for reasons of power and speed. These systems have to support a large number of applications and standards, in different combinations, called use-cases. The key challenges are designing efficient systems handling all these usecases; this requires fast exploration of software and hardware alternatives with accurate performance evaluation. In this paper, we present a system-level FPGA-based simulation methodology for performance evaluation of applications on multiprocessor platforms. We observe that for multiple applications sharing an MPSoC platform, dynamic arbitration can cause deadlock in simulation. We use conservative Parallel Discrete Event Simulation (PDES) for simulation of these use-cases. We further note that conservative PDES is inefficient so we present a new PDES methodology that avoids causality errors by detecting them in advance. We call our new approach as smart conservative PDES. It is scalable in the number of use-cases and number of simulated processors and is 15% faster than conservative PDES. We further present results of a case-study of two real life applications. We used our simulation technique to do a design space exploration for optimal buffer space for JPEG and H263 decoders.

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MPARM: Exploring the Multi-Processor SoC Design Space with SystemC

Cited by 206 publications

References 12 publications

A unified online directed acyclic graph flow manager for multicore schedulers

A unified online directed acyclic graph flow manager for multicore schedulers

Fast and cycle-accurate modeling of a multicore processor

Performance evaluation of concurrently executing parallel applications on multi-processor systems

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