Fast and cycle-accurate modeling of a multicore processor

Khan, Asif; Vijayaraghavan, Muralidaran; Boyd-Wickizer, Silas; Arvind, .

doi:10.1109/ispass.2012.6189224

Cited by 20 publications

(11 citation statements)

References 24 publications

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“…However, there is no reason for those models to continue being valid when new features are added to the system [13], which is the purpose of computer architecture research. We believe that 1) and 3) question the suitability of fast, noncycle-accurate software tools for new architectural research proposals.…”

Section: B Software Simulatorsmentioning

confidence: 99%

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High-Level Debugging and Verification for FPGA-Based Multicore Architectures

Arcas-Abella

Cristal

Unsal

2015

2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines

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Abstract-Simulators are key tools for computer architecture research. However, multicore architectures represent a highly complex challenge for software simulators, which may suffer from fidelity loss and long execution times. FPGAs can simulate multicore architectures with scalable performance and high accuracy, but the difficulty of debugging could hinder their adoption.In this paper we propose several techniques for inspection, debugging and verification of multicore architectures, both for software-based and FPGA-based simulations. These debugging extensions are cycle-accurate and unobtrusive. As a proof of concept, we have developed a 24-core RISC multiprocessor that runs the Linux Kernel, for which we provide three simulation modes: a fast, functional simulation; a detailed, cycle-accurate simulation; and a FPGA-based simulation. Our platform can run up to 24 cores and perform full-system verification at 17 million instructions per second.

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Section: B Software Simulatorsmentioning

confidence: 99%

“…That is the case of RAMP Gold [17] and FAST [18]. In contrast, HaSim [19] and Arete [13] use A-Ports or Latency-Insensitive Bounded Data-flow Networks, which decouple FPGA cycles from model cycles while guaranteeing cycle-accuracy. HaSim uses time multiplexing, which does not scale.…”

Section: Fpga-based Multicores and Simulatorsmentioning

confidence: 99%

High-Level Debugging and Verification for FPGA-Based Multicore Architectures

Arcas-Abella

Cristal

Unsal

2015

2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines

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“…Despite recent progress on fast and general FPGA-based simulators [12,19,31,47], these frameworks require substantial investment in specialized multi-FPGA boards [50] and are difficult to use for architectural exploration as they involve complex FPGA toolchains with hours-long compiles. Consequently, we focus on software-based simulation.…”

Section: Simulation Techniquesmentioning

confidence: 99%

ZSim

Sánchez

Kozyrakis

2013

Proceedings of the 40th Annual International Symposium on Computer Architecture

314

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Architectural simulation is time-consuming, and the trend towards hundreds of cores is making sequential simulation even slower. Existing parallel simulation techniques either scale poorly due to excessive synchronization, or sacrifice accuracy by allowing event reordering and using simplistic contention models. As a result, most researchers use sequential simulators and model small-scale systems with 16-32 cores. With 100-core chips already available, developing simulators that scale to thousands of cores is crucial.We present three novel techniques that, together, make thousand-core simulation practical. First, we speed up detailed core models (including OOO cores) with instructiondriven timing models that leverage dynamic binary translation. Second, we introduce bound-weave, a two-phase parallelization technique that scales parallel simulation on multicore hosts efficiently with minimal loss of accuracy. Third, we implement lightweight user-level virtualization to support complex workloads, including multiprogrammed, client-server, and managed-runtime applications, without the need for full-system simulation, sidestepping the lack of scalable OSs and ISAs that support thousands of cores.We use these techniques to build zsim, a fast, scalable, and accurate simulator. On a 16-core host, zsim models a 1024-core chip at speeds of up to 1,500 MIPS using simple cores and up to 300 MIPS using detailed OOO cores, 2-3 orders of magnitude faster than existing parallel simulators. Simulator performance scales well with both the number of modeled cores and the number of host cores. We validate zsim against a real Westmere system on a wide variety of workloads, and find performance and microarchitectural events to be within a narrow range of the real system.

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“…Using the LI-BDN-based debugging methodology described in Section IV, we built a comprehensive debugging facility for Arete [9], which is an FPGA-based cycle-accurate multicore simulator. Arete may be implemented as a distributed multicore simulator on a multi-FPGA platform, which requires the debugging infrastructure to be implemented in a distributed manner.…”

Section: Studymentioning

confidence: 99%

“…The main contributions of this paper are 1) a technique for building a deterministic model-cycle-level debugging infrastructure, based on the LI-BDN modeling methodology, and 2) an application of the technique to build a comprehensive debugging infrastructure for Arete [9], which is an FPGA-based multicore processor simulator.…”

Section: Introductionmentioning

confidence: 99%

A general technique for deterministic model-cycle-level debugging

Khan

Vijayaraghavan

Arvind

2012

Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMCODE2012)

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Abstract-Efficient use of FPGA resources requires FPGA-based performance models of complex hardware to implement one model cycle, i.e., one time-step of the original synchronous system, in several implementation cycles. Generally implementation cycles have no simple relationship with model cycles, and it is tricky to reconstruct the state of the synchronous system at the modelcycle boundaries if only implementation-cycle-level control and information is provided. A good debugging facility needs to provide: complete control over the functioning of the target design being simulated; fast and easy access to all the significant target design state for both monitoring and modification; and some means of accomplishing deterministic execution when the target design is a multicore processor running a parallel application. Moreover, these features need to be provided in a manner which does not incur substantial resource and performance penalties.In this paper, we present a debugging technique based on the LI-BDN theory. We show how the technique facilitates deterministic model-cycle-level debugging. We used it to build the debugging infrastructure for Arete, which is an FPGA-based cycle-accurate multicore simulator. The resource and performance penalties of our debugging technique are minimal; in Arete the debugging infrastructure has area and performance overheads of 5% and 6%, respectively.

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Fast and cycle-accurate modeling of a multicore processor

Cited by 20 publications

References 24 publications

High-Level Debugging and Verification for FPGA-Based Multicore Architectures

High-Level Debugging and Verification for FPGA-Based Multicore Architectures

ZSim

A general technique for deterministic model-cycle-level debugging

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