Abstract:Abstract-Efficient use of FPGA resources requires FPGA-based performance models of complex hardware to implement one model cycle, i.e., one time-step of the original synchronous system, in several implementation cycles. Generally implementation cycles have no simple relationship with model cycles, and it is tricky to reconstruct the state of the synchronous system at the modelcycle boundaries if only implementation-cycle-level control and information is provided. A good debugging facility needs to provide: com… Show more
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