A compact model of MOSFET mismatch for circuit design

Galup-Montoro, Carlos; Schneider, M.C.; Klimach, Hamilton; Arnaud, Alfredo

doi:10.1109/jssc.2005.852045

Cited by 44 publications

(8 citation statements)

References 46 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…From [18], the small signal transconductance is related to the forward inversion level as follows Substituting Eqs. (20) and (28) in (27) and after some algebra, we get 30which defines the GZTC condition. The i fgz is defined as GZTC forward inversion level.…”

Section: B Mosfet Transconductance Ztc Conditionmentioning

confidence: 99%

See 1 more Smart Citation

Low Temperature Sensitivity CMOS Transconductor Based on GZTC MOSFET Condition

Toledo¹,

Klimach²,

Cordova³

et al. 2020

JICS

View full text Add to dashboard Cite

Complementary Metal Oxide Semiconductor (CMOS) Transconductors, or Gm cells, are key building blocks to implement a large variety of analog circuits such as adjustable filters, multipliers, controlled oscillators and amplifiers. Usually temperature stability is a must in such applications, and herein we define all required conditions to design low thermal sensitivity Gm cells by biasing MOSFETs at Transconductance Zero Temperature Condition (GZTC). This special bias condition is analyzed using a MOSFET model which is continuous from weak to strong inversion, and it is proved that this condition always occurs from moderate to strong inversion operation in any CMOS fabrication process. Additionally, a few example circuits are designed using this technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits have been simulated in a 130 nm CMOS commercial process, resulting in improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/oC.

show abstract

Section: B Mosfet Transconductance Ztc Conditionmentioning

confidence: 99%

“…24, (25) Replacing I S , or Eq. (4), in Eq (25) (26) Or, (27) The term (μ(T)ϕ t (T)) can be found using = and = from [22],…”

Section: B Mosfet Transconductance Ztc Conditionmentioning

confidence: 99%

Low Temperature Sensitivity CMOS Transconductor Based on GZTC MOSFET Condition

Toledo¹,

Klimach²,

Cordova³

et al. 2020

JICS

View full text Add to dashboard Cite

show abstract

“…Therefore, we can analyze the effects of DC mismatch by simulating the effects of the equivalent AC noise instead. Interestingly, Galup-Montoro, et al [24] demonstrated that the model equations for the transistor current mismatch can be derived based on the carrier number fluctuation theory which underlies the 1/f flicker noise. In essence, the mismatch and the 1/f flicker noise may share the same physical explanations except that one is spatial fluctuation while the other is temporal.…”

Section: Sensitivity-based Mismatch Analysis Via Lptv Noise Simulmentioning

confidence: 99%

Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch

Kim

Jones

Horowitz

2010

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

show abstract

“…Also known as device mismatch, these type of process variations are dominated mostly by random dopant fluctuation (RDF) in the transistor channel, local grain fluctuations in the gate workfunction, and the line edge roughness (LER) at the edges of the gate of the transistor [3]. The main characteristic on WID variation is that it fluctuates randomly and independently from device to device and it increases when the transistor size decreases [4], [16]. This paper shows the impact of WID and D2D parameter variation in CMOS ring oscillators through silicon measurements on 65 nm CMOS process.…”

Section: Introductionmentioning

confidence: 99%

Within-die and die-to-die variability on 65nm CMOS : oscillators experimental results

Brito¹,

Lubaszewski²,

Bampi

2015

2015 International Workshop on CMOS Variability (VARI)

View full text Add to dashboard Cite

This paper presents experimental data and analyses from the oscillation frequency of CMOS ring oscillators (ROs). The measurements are analyzed in order to separate the coefficient of variation (CV = σ/µ) behavior of both within-die (WID) process variations and Die-to-Die (D2D) process variations. Three different RO's sizes distributed over a total of 96 ROs per chip were measured in 32 different chip samples, all from a single MOSIS Multi-Project-wafer in a commercial 65nm CMOS process. All ROs were measured with varying power supply voltages, from nominal VDD (1.2V) down to nearthreshold (0.45V), resulting in a sample space of 18.432 points of interest. Statistical analysis results are shown regarding each RO stage size, the applied power supply and the correlation of both to the WID and D2D variations. The increase on D2D and WID coefficients of variations at the near-threshold supplies is very significant, as explained by increased delay variability at the moderate inversion regime of the FETs. The 96 test ROs occupy a total area of 200 x 480 µm 2 in each test chip.

show abstract

A compact model of MOSFET mismatch for circuit design

Cited by 44 publications

References 46 publications

Low Temperature Sensitivity CMOS Transconductor Based on GZTC MOSFET Condition

Low Temperature Sensitivity CMOS Transconductor Based on GZTC MOSFET Condition

Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch

Within-die and die-to-die variability on 65nm CMOS : oscillators experimental results

Contact Info

Product

Resources

About