A Cmos Electrically Configurable Gate Array

EI-Ajat,; Guo, Youguang; Chang,; Hamdy,; McCollum,; Mohsen, Mohsen

doi:10.1109/isscc.1988.663633

Cited by 12 publications

(7 citation statements)

References 2 publications

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“…Such models are exemplified by the Actel family of FPGAs [9,10]. We review the basic architecture of the array and then discuss the routing issues.…”

Section: Row-based Fpga Modelmentioning

confidence: 99%

A survey of DA techniques for PLD and FPGA based systems

Venkateswaran

Mazumder

1994

Integration

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Programmable logic devices (PLDs) are gaining in acceptance, of late, for designing systems of all complexities ranging from glue logic to special purpose parallel machines. Higher densities and integration levels are made possible by the new breed of complex PLDs and FPGAs. The added complexities of these devices make automatic computer aided tools indispensable for achieving good performance and a high usable gate-count. In this article, we attempt to present in an unified manner, the different tools and their underlying algorithms using an example of a vending machine controller as an illustrative example. Topics covered include logic synthesis for PLDs and FPGAs along with an in-depth survey of important technology mapping, partitioning and place and route algorithms for different FPGA architectures.

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“…Such models are exemplified by the Actel family of FPGAs [9,10]. We review the basic architecture of the array and then discuss the routing issues.…”

Section: Row-based Fpga Modelmentioning

confidence: 99%

A survey of DA techniques for PLD and FPGA based systems

Venkateswaran

Mazumder

1994

Integration

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“…Figure 1 illustrates the channeled field programmable gate array architecture. Commercially such FPGAs are available from Actel [4,8,7]. There are various programming technologies available and each has its own advantages and disadvantages.…”

Section: Introductionmentioning

confidence: 99%

Greedy Segmented Channel Router

Bhatia

Shankar

1996

VLSI Design

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An efficient solution to the generalized detailed routing problem in segmented channels for row-based FPGAs is presented. A generalized detailed routing allows routing of each connection using an arbitrary number of tracks, i.e., doglegs are allowed. This approach is different from the normally followed method where each connection is routed on a single straight track. We present a router that performs generalized segmented channel routing using a greedy approach to route channels. The router also renders itself to limited tolerance against faults in the routing architecture.

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“…Actel FPGAs use an indirect addressing scheme to apply V, , and Ov to the target antifuse electrodes (see Figure 2(a)) after precharge to Vpp/2 [4]. V, , is supplied to the target antifuse vertical wire indirectly through adjacent vertical wires connected by pass transistors.…”

Section: Select (Address) and Drive The Vertical (Horizontal) Wirementioning

confidence: 99%

Programming antifuses in Crosspoint's FPGA

Mafple¹,

Cooke²

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94

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This paper describes how Crosspoint programs antifuses in its fine grain architecture. It compares the programming circuits used by Crosspoint to the circuits used by Actel and Quicklogic. Every antifuse in Crosspoint's FPGA can be uniquely programmed using a three dimensional addressing scheme to independently drive each electrode of the antifuse. The circuitry supports 10 volt programming and 13.5ma programming current to any target antifuse. Although the programming overhead is high, the antifuses are programmed to an average 50 Cl resistance, thus providing for high performance operation of the FPGA.

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A Cmos Electrically Configurable Gate Array

Cited by 12 publications

References 2 publications

A survey of DA techniques for PLD and FPGA based systems

A survey of DA techniques for PLD and FPGA based systems

Greedy Segmented Channel Router

Programming antifuses in Crosspoint's FPGA

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