A CMOS 7Gb/s, 4-PAM and 4-PWM, serial link transceiver

Abstract

This paper proposes a new multi level of amplitude and pulse width (PW) modulation structure for a 7Gb/s serial link transceiver. This scheme can be implemented in 0.18 m CMOS technology. Applying this technique, 7 bit data is embedded in a symbol time. Therefore the symbol rate is reduced, while the minimum PW is increased. In the proposed structure, the PW is larger than Tb (a conventional NRZ data PW). Therefore, the ISI will be improved. The multiphase output of a five stage ring oscillator VCO in the PLL is used to modulate and demodulate the signal. In PAM modulator block, a current-mode technique is used to increase the rate of data transmission. Serialization of parallel data is established by a current-mode multiplexer. At the receiver part, a novel high-speed comparator is proposed to demodulate the data signal. In addition, to reinforce the incoming signal, a preamplifier with high gain and high bandwidth is proposed. PWAM modulator, which consists of a PWM modulator and a PAM modulator blocks, consumes 71 mW. The receiver block power consumption is about 14 mW.

A 12‐Gb/s serial link transceiver using dual‐mode pulse amplitude modulation scheme in a 0.18‐μm CMOS process

“…Also, unlike the transceiver proposed in, 9 which has the non‐return to zero data format and needs a complex clock recovery system, this work benefits from an easy clock recovery system employing a simple conventional PLL. The transceivers in Ghaderi et al 5 and Mostafa, 8 modulate the signal width according to the input bits, which minimizes MPW and results in more ISI, limiting the highest achievable data rate.…”

“…Pulse-width-amplitude modulation (PWAM), which is a combination of PWM and PAM techniques, can achieve a higher data transfer rate using a simplified scheme and pin-count reduction. 4,5 Data and clock channels are combined in this modulation to create an individual channel and the raw binary data is also coded into pulses with different widths and a periodic rising edge. This allows the clock signal to be recovered by using a simple PLL at the receiver.…”

“…The other pulse‐modulation techniques include pulse‐width modulation (PWM), pulse‐phase modulation (PPM), and pulse‐density modulation (PDM). Pulse‐width‐amplitude modulation (PWAM), which is a combination of PWM and PAM techniques, can achieve a higher data transfer rate using a simplified scheme and pin‐count reduction 4,5 . Data and clock channels are combined in this modulation to create an individual channel and the raw binary data is also coded into pulses with different widths and a periodic rising edge.…”

A Dual Modulation Pulse Position Modulation Approach in 130nm Cmos Technology for Time Based Serial Communication Links

“…Using a PLL for generating time-shifted sampling clocks complicates the design especially at high frequencies. In [7],the PWM technique has been combined with the PAM technique in order to increase the number of the data bits and as a result increasing the data rate of the transmitted data signal. So that the authors achieved high data rate transfer using both PWM and PAM (PWAM) schemes.…”

On Optimization of Manufacturing of a Comparator in Track State to Increase Integration Rate of Elements

“…An actual and intensively studied topic in solid-state electronics is the need for increasing the integration rate of elements of integrated circuits (p-n-junctions, their systems, etc.) [1][2][3][4][5][6][7][8]. Increasing the integration rate leads to a necessity to decrease their dimensions.…”