In this article, a 3.2 Gb/s serial link transceiver, that can be implemented in 0.35 lm CMOS technology is presented. In this transceiver a new multi-level pulsewidth-amplitude modulation technique is used. The symbol rate is reduced, while the minimum pulse width (PW) is increased considerably, using the proposed modulation. The PW is larger than the conventional NRZ data format, with PW of Tb, so the ISI will be improved. The multiphase output of a three stage ring oscillator VCO in the PLL is used to modulate and to demodulate the signal. A new charge pump circuit is also introduced to decrease the mismatch between up and down paths. The peak to peak jitter of recovered clock is 21 ps at 800 MHz. The recovered data has the peak to peak jitter of 51 ps. The transmitter and receiver power consumption is 220 and 35 mW, respectively.
Background: The thermal conductivity of fluids can be calculated by several computational methods. However, these methods are reliable only at the confined levels of density, and there is no specific computational method for calculating thermal conductivity in the wide ranges of density.Methods: In this paper, two methods, an Artificial Neural Network (ANN) approach and a computational method established upon the Rainwater-Friend theory, were used to predict the value of thermal conductivity in all ranges of density. The thermal conductivity of six refrigerants, R12, R14, R32, R115, R143, and R152 was predicted by these methods and the effectiveness of models was specified and compared.Results: The results show that the computational method is a usable method for predicting thermal conductivity at low levels of density. However, the efficiency of this model is considerably reduced in the mid-range of density. It means that this model cannot be used at density levels which are higher than 6. On the other hand, the ANN approach is a reliable method for thermal conductivity prediction in all ranges of density. The best accuracy of ANN is achieved when the number of units is increased in the hidden layer.Conclusion: The results of the computational method indicate that the regular dependence between thermal conductivity and density at higher densities is eliminated. It can develop a nonlinear problem. Therefore, analytical approaches are not able to predict thermal conductivity in wide ranges of density. Instead, a nonlinear approach such as, ANN is a valuable method for this purpose.
This paper proposes a new multi level of amplitude and pulse width (PW) modulation structure for a 7Gb/s serial link transceiver. This scheme can be implemented in 0.18 m CMOS technology. Applying this technique, 7 bit data is embedded in a symbol time. Therefore the symbol rate is reduced, while the minimum PW is increased. In the proposed structure, the PW is larger than Tb (a conventional NRZ data PW). Therefore, the ISI will be improved. The multiphase output of a five stage ring oscillator VCO in the PLL is used to modulate and demodulate the signal. In PAM modulator block, a current-mode technique is used to increase the rate of data transmission. Serialization of parallel data is established by a current-mode multiplexer. At the receiver part, a novel high-speed comparator is proposed to demodulate the data signal. In addition, to reinforce the incoming signal, a preamplifier with high gain and high bandwidth is proposed. PWAM modulator, which consists of a PWM modulator and a PAM modulator blocks, consumes 71 mW. The receiver block power consumption is about 14 mW.
Abstract:In this article a novel charge pump circuit is introduced. The proposed circuit utilizes a bulk driven cascode current mirror through an adaptive gate bias technique, that results in a high output impedance over a very wide output voltage range, accurate Charge/ Discharge current matching, which minimizes the steady-state phase error in a phase-locked loop (PLL), and low transient glitches. The current variation is less than 0.5 μA or 1% over output range. Therefore proposed circuit stabilizes the loop bandwidth of the charge pump PLL and maximizes the dynamic range. The charge pump is designed and simulated under the power supply of 1.8 V in 0.18 μm CMOS technology to verify the efficiency of the proposed techniques. Monte Carlo process variations and mismatch simulations show that the current variation in the proposed charge pump is very low.
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