A CMOS 12K gate array with flexible 10Kb memory

Takechi, Makoto; Ikuzaki, K.; Itoh, Takaò; Fujita, Motomichi; Asano, M.; Masaki, Akira; Matsunaga, T.

doi:10.1109/isscc.1984.1156670

Cited by 9 publications

(2 citation statements)

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“…In the past, gate arrays [9,10] have been used as an implementation method in which a design can be personalized via and metal customization. This approach was popular until standard cell based design became the dominant means to design ICs.…”

Section: Previous Workmentioning

confidence: 99%

A lithography-friendly structured ASIC design approach

Gopalani

Garg

Khatri

et al. 2008

Proceedings of the 18th ACM Great Lakes Symposium on VLSI

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Integrated circuit manufacturing costs are increasing with decreasing device feature sizes, due to significant increases in mask costs. At the same time, systematic processing variations due to optical proximity effects are also increasing, making it harder to predict the circuit behavior with fidelity. Therefore, there is a need to implement designs using regular circuit structures. In this paper, we present a new structured ASIC approach which utilizes an array of 2-input NAND gates. Our NAND2 array based circuit implementation reduces manufacturing costs, and design turn-around times because different designs can share the same masks up to the poly layer. The regular layout structure of our NAND2 array also helps in reducing systematic variations. We compared the performance of our NAND2 array with the ASIC approach by implementing several benchmark circuits using both methods. The experimental results demonstrate that on average, our approach has a delay penalty of 40%, an area penalty of 12%, and a power increase of 7%, compared to an ASIC design approach. This is better than the previously reported structured ASIC approaches. We also performed lithographical simulations of the poly and metal masks of the designs implemented using our approach as well as the ASIC design approach. These lithographical simulation results demonstrate that our approach has lower errors on the poly and the Metal1 layers by 7% and 24% respectively, compared to the ASIC approach.

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Section: Previous Workmentioning

confidence: 99%

A lithography-friendly structured ASIC design approach

Gopalani

Garg

Khatri

et al. 2008

Proceedings of the 18th ACM Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

show abstract

“…The number of logic circuits on CMOS gate array chips have increased with time [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20]. Gate array chips have transistor assemblages on "lattice" positions.…”

Section: Historical Backgroundmentioning

confidence: 99%

Challenges in advanced semiconductor technology for high-performance and supercomputer applications

Osburn

Reisman

1987

J Supercomput

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This article provides a review of the capabilities, future directions, and technology challenges for semiconductor chips and packages as they apply to high-performance and supercomputer applications. Semiconductor chip technology has resulted in dramatic device density improvements over the last 20 years. Scaling theory predicts that continued improvements will be possible if the technological problems associated with patterning, doping, interconnection, density, yield, and cost can be solved. The issues associated with these challenges are discussed. Finally, the packaging needs to support advanced chip technologies are reviewed.

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Challenges in advanced semiconductor technology in the ulsl era for computer applications

Osburn

1987

J. Electron. Mater.

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A CMOS 12K gate array with flexible 10Kb memory

Cited by 9 publications

References 1 publication

A lithography-friendly structured ASIC design approach

A lithography-friendly structured ASIC design approach

Challenges in advanced semiconductor technology for high-performance and supercomputer applications

Challenges in advanced semiconductor technology in the ulsl era for computer applications

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