A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS

Karnik, Tanay; Kurian, Dileep; Aseron, Paolo; Dorrance, Richard; Alpman, Erkan; Nicoarã, Angela; Popov, Roman; Azarenkov, Leonid; Moiseev, Mikhail; Zhao, Li; Ghosh, Santosh; Misoczki, Rafael; Gupta, Ankit; Akhila, M; Muthukumar, Sriram; Bhandari, Saurabh; Yada, Satish; Jain, Kartik; Flory, Robert; Kanthapanit, Chanitnan; Quijano, Eduardo; Jackson, Brad R.; Luo, Hao; Kim, Suhwan; Vaidya, Vaibhav; Elsherbini, A.; Liu, Renzhi; Sheikh, Farhana; Tickoo, Omesh; Klotchkov, Ilya; Sastry, Manoj; Sun, Sheldon; Bhartiya, Mukesh; Srinivasan, Anuradha; Hoskote, Yatin; Wang, Hong; De, Vivek

doi:10.1109/isscc.2018.8310176

Cited by 38 publications

(14 citation statements)

References 1 publication

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“…In addition, energy per cycle do not take the performance, architecture, and gate count into account, but for reference, this table gives pJ/cycle of each chip. Most SoCs in the previous work rely on a bus-based interconnect system [10], [13], [24], while a combination of bus and NoC architectures is used in a recent work [14]. In the table, only the previous work in [24] exploits the TEI phenomenon without any consideration of the on-chip interconnects, because only a few IPs are connected to the system bus which does not induce a long wire structure.…”

Section: B Power Savings On Chipsmentioning

confidence: 99%

Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes

Han

Lee

et al. 2021

IEEE Internet Things J.

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Ranging from circuit-level characterization to designing a platform architecture, developing a design automation tool, and fabricating a System on Chip (SoC), this article deals with the entire development process for ultralow-power (ULP) SoCs for Internet-of-Things (IoT) end nodes. More precisely, this article first focuses on the unique characteristics of the ULP circuits, the temperature effect inversion (TEI), i.e., the delay of the ULP circuits decreases with increasing temperature. Existing TEI-aware low-power (TEI-LP) techniques have incredible potential to further reduce the power consumption of conventional ULP SoCs, but there is a critical limitation to be widely adopted in real SoCs. To address this limitation and realize the ULP SoCs that can fully benefit from the TEI-LP techniques, this article proposes a new TEI-inspired SoC platform (TIP) architecture. On top of that, taking into account that the highly complex, time consuming, and labor-intensive development process of these ULP SoCs may hinder their widespread use for IoT end nodes, this article presents a new electronic design automation tool to accelerate ULP SoC development, RISC-V express (RVX). Finally, by using the RVX, this article introduces a TIP prototyping chip fabricated in 28-nm FD-SOI technology. This chip demonstrates that power savings of up to 35% can be achieved by lowering the supply voltage from 0.54 to 0.48 V at 25 • C and 0.44 V at 80 • C while continuing to operate at a target 50-MHz clock frequency.

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Section: B Power Savings On Chipsmentioning

confidence: 99%

Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes

Han

Lee

et al. 2021

IEEE Internet Things J.

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“…The traditional node architectures, where 8-bit microcontrollers were the main core of the sensor platforms for performing simple acquisition tasks, are evolving towards more sophisticated microprocessors and System on Chip that provide enhanced trade-off solutions between processing capabilities and power consumption [16]. However, since the effective duty cycle and energy demand of these devices are also increasing in line with their computational load (and thus the network lifetime will anyway be penalized), they are rather planned to be deployable platforms with accessible external power sources in most of the real application cases.…”

Section: A Edge Computingmentioning

confidence: 99%

The Extreme Edge at the Bottom of the Internet of Things: A Review

et al. 2019

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resources (e.g., networks, servers, storage, applications, and services) that can be rapidly provisioned and released with minimal management effort or service provider interaction. This general definition shows the power that cloud computing makes available to the Internet of Things. The basic idea is to collect information, usually big amounts of data, in the point of interest (this so-called the edge, where information is generated) and upload it to be properly processed in the cloud, where ideally permanent and enough processing resources are available. This model may work perfectly with some approaches where the energy resource is not a limitation or the time required for any decision does not impose a very fast reaction. However, the cloud computing paradigm applied directly to IoT presents a set of drawbacks regarding latency, bandwidth and storage [10] because of the huge amount of data that have to be uploaded and processed. Due to these limitations, more layers have been proposed during the last years, getting closer to the source of data.

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“…Extending end-node devices with accelerators dedicated to specialized functions can significantly improve energy efficiency for these specific tasks, while leveraging general purpose processors for other tasks. This approach has been effectively adopted in secure artificial intelligence processors featuring Convolutional Neural Network (CNN) accelerators for data analytics and crypto accelerators for security [12] [13] [14]. A much more flexible solution lies in Parallel Near Threshold Computing.…”

Section: Introductionmentioning

confidence: 99%

Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing

Pullini

Rossi

Loi

et al. 2019

IEEE J. Solid-State Circuits

105

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This paper presents Mr.Wolf, a Parallel Ultra Low Power (PULP) SoC featuring a hierarchical architecture with a small (12 kgates) microcontroller (MCU) class RISC-V core augmented with an autonomous IO subsystem for efficient data transfer from a wide set of peripherals. The small core can offload compute-intensive kernels to an 8-cores floating-point capable processing engine available on demand. The proposed SoC, implemented in a 40 nm LP CMOS technology, features a 108 µW fully retentive memory (512 kB). The IO subsystem is capable of transferring up to 1.6 Gbit/s from external devices to the memory in less than 2.5 mW. The 8-core compute cluster achieves a peak performance of 850 millions of 32-bit integer multiply and accumulate per second (MMAC/s), 500 millions of 32-bit floating-point multiply and accumulate per second (MFMAC/s)-1 GFlop/s-with an energy efficiency up to 15 MMAC/s/mW and 9 MFMAC/s/mW. These building blocks are supported by aggressive on-chip power conversion and management, enabling energy-proportional heterogeneous computing for always-on IoT end-nodes improving performance by several orders of magnitude with respect to traditional single core MCUs within a power envelope of 153 mW. We demonstrated the capabilities of the proposed SoC on a wide set of near-sensor processing kernels showing that Mr.Wolf can deliver performance up to 16.4 GOp/s with energy efficiency up to 274 MOp/s/mW on reallife applications, paving the way for always-on data analytics on high-bandwidth sensors at the edge of the Internet of Things.

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A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS

Cited by 38 publications

References 1 publication

Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes

Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes

The Extreme Edge at the Bottom of the Internet of Things: A Review

Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing

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