A chip-package-board co-design methodology

Tsai

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

et al. 2014

In current chip and package designs, it is a bottleneck to simultaneously optimize both pin assignment and pin routing for different design domains (chip, package, and board). Usually the whole process costs a huge manual effort and multiple iterations thus reducing profit margin. Therefore, we propose a fast heuristic chip-package co-design algorithm in order to automatically obtain a bump assignment which introduces high routability both in RDL routing and substrate routing (100% in our real case). Experimental results show that the proposed method (inspired by board escape routing algorithms) automatically finishes bump assignment, RDL routing and substrate routing in a short time, while the traditional co-design flow requires weeks even months.

Section: A Previous Workmentioning

confidence: 99%

“…Furthermore, the main reason that causes the bottleneck of co-design problem is the iteration of design process. Therefore, [12] provided a board-driven Λ-shaped co-design flow with true bi-directional information interactions and [13] offered a concurrent design flow to avoid much longer turn-around time.…”

Section: A Previous Workmentioning

confidence: 99%

Routability-driven bump assignment for chip-package co-design

Tsai

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

“…After the floorplan of dies is determined, a network-flowbased signal assignment algorithm is proposed to assign signals to macro-bumps and TSVs and minimize the total wirelength in a 2.5D IC. Different from the traditional SAPs [6,7] with only a single die, the proposed algorithm assigns signals to the micro-bumps of multiple dies and TSVs in the interposer. Also, a window matching method is presented to speed up the proposed signal assignment algorithm.…”

Section: Introductionmentioning

confidence: 99%

Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs

Liu

Chang

Wang

2014

Interposer-based 3D ICs (or known as 2.5D ICs) have been seen as an alternative approach to true 3D stacked ICs, which mount multiple dies on a silicon interposer and route signals between dies by the interconnects in the interposer. However, the floorplan of dies on the interposer and the signal assignment for macro-bumps and TSVs will largely impact the wirelength of the interconnects in a 2.5D IC. Because long interconnects would degrade the performance of 2.5D ICs, the multi-die floorplanning problem and signal assignment problem for 2.5D ICs are critical. This paper presents an enumeration-based algorithm and a network-flow-based algorithm to solve the multi-die floorplanning and signal assignment problems in a 2.5D IC, respectively. Also, to speed up the floorplanning and signal assignment algorithms, several acceleration techniques are proposed. The experimental results reveal that this work can effectively reduce the total wirelength in a 2.5D IC and the acceleration techniques can significantly speed up the proposed algorithms.

Proceedings of the 50th Annual Design Automation Conference

“…The inter-chip connections of this result are shorter and simpler than that in Figure 2 consume fewer layers and vias in a standard interposer and thus improve its signal quality and reduce the manufacturing cost. Many previous works have addressed various codesign problems as follows: (1) chip-package codesign [5,6,13,17,18,21,23], (2) package-board codesign [8,16], and (3) chip-packageboard codesign [7,15,20]. However, no previous work is focused on silicon interposers, key components of interposer-based 3D ICs.…”

Section: Introductionmentioning

confidence: 99%

“…For the chip-package-board codesign problem, Park [20] proposed a die abstract model and a board-driven methodology to reduce the overall design cycle and cost. Lee and Chang [15] proposed a Λ-shaped codesign flow to route signals among boards, packages, and chips. To consider differential pairs, an integer linear programming (ILP) based routing algorithm was proposed in [7].…”

Section: Introductionmentioning

confidence: 99%

Multiple chip planning for chip-interposer codesign

Chang

2013

Self Cite

An interposer-based three-dimensional integrated circuit, which introduces a silicon interposer as an interface between chips and a package, is one of the most promising integration technologies for modern and next-generation circuit designs. Inter-chip connections can be routed on the interposer by chip-scale wires to enhance design quality. However, its design complexity increases dramatically due to the extra interposer interface. Consequently, it is desirable to simultaneously consider the co-design of the interposer and multiple chips mounted on it. This paper addresses the first work of chip-interposer codesign to place multiple chips on an interposer to reduce inter-chip wirelength. For this problem, we propose a new hierarchical B*-tree to simultaneously place multiple chips, macros, and I/O Buffers. An approach based on bipartite matching is then proposed to concurrently assign signals from I/O buffers to micro bumps. Experimental results show that our approach is effective and efficient for the codesign problem.