A Cavity Chip Interconnection Technology for Thick MEMS Chip Integration in MEMS-LSI Multichip Module

Lee, Kangwook; Kanno, Shigenori; Kiyoyama, K.; Fukushima, T.; Tanaka, Tetsu; Koyanagi, Mitsumasa

doi:10.1109/jmems.2010.2082497

Cited by 24 publications

(5 citation statements)

References 17 publications

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“…1% HF solution can precisely and quickly align many KGDs on host wafers at once within 0.1 sec with an alignment accuracy of below 500 nm, and at the same time, the KGDs can be tightly bonded on the corresponding wafers through thermal oxide layers. The HF assisted oxide-oxide direct bonding is applicable to CMP-treated PE-CVD oxide (2), ( 26)- (27). Nowadays, pure water can be used for the direct oxide-oxide bonding although plasma-and water-assisted thermal compression bonding is required (28), (29).…”

Section: Bumpless Bondingmentioning

confidence: 99%

(Invited) Self-Assembly Based Multichip-to-Wafer Bonding Technologies for 3D/Hetero Integration

Fukushima¹,

Lee²,

Tanaka³

et al. 2016

ECS Trans.

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We have proposed and developed 3D integration technologies based on self-assembly using surface tension of liquid in this decade. In this paper, microbump bonding and bumpless bonding in face-up and/or face-down configuration are introduced for fine-pitch interconnect formation. In addition, “non-transfer stacking”, in other word, flip-chip self-assembly and “transfer stacking” called reconfigure-wafer-to-wafer using SAE carrier are explained.

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Section: Bumpless Bondingmentioning

confidence: 99%

(Invited) Self-Assembly Based Multichip-to-Wafer Bonding Technologies for 3D/Hetero Integration

Fukushima¹,

Lee²,

Tanaka³

et al. 2016

ECS Trans.

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“…4), 23,24) the integration of MEMS chip on CMOS chip by chip self-assembly and sidewall interconnection technologies (Fig. 5), 25,26) and the integration of an optoelectronic chip on a CMOS chip (Fig. 6).…”

Section: -D Heterogeneous Opto-electronics Integration Technologymentioning

confidence: 99%

3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

Lee¹

2015

Journal of the Microelectronics and Packaging Society

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Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore`s law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

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“…31 s after dropping the cavity chip onto the substrate, the chip was aligned and then bonded to the target bonding region. In our previous study, average alignment accuracy was kept constant at approximately 1 m when we employed a liquid droplet ranging in volume from 0.3 l to 1.8 l for self-assembly of 3 mm square chips [30]. The accuracy was not highly sensitive to the liquid volume in the 0.3 l to 1.8 l region.…”

Section: Chip and Substrate Fabricationmentioning

confidence: 99%

Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration

et al. 2011

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New surface mounting and packaging technologies, using self-assembly with chips having cavity structures, were investigated for three-dimensional (3D) and hetero integration of complementary metal-oxide semiconductors (CMOS) and microelectromechanical systems (MEMS). By the surface tension of small droplets of 0.5 wt% hydrogen fluoride (HF) aqueous solution, the cavity chips, with a side length of 3 mm, were precisely aligned to hydrophilic bonding regions on the surface of plateaus formed on Si substrates. The plateaus have micro-channels to readily evaporate and fully remove the liquid from the cavities. The average alignment accuracy of the chips with a 1 mm square cavity was found to be 0.4 mm. The alignment accuracy depends, not only on the area of the bonding regions on the substrates and the length of chip periphery without the widths of channels in the plateaus, but also the area wetted by the liquid on the bonding regions. The precisely aligned chips were then directly bonded to the substrates at room temperature without thermal compression, resulting in a high shear bonding strength of more than 10 MPa

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A Cavity Chip Interconnection Technology for Thick MEMS Chip Integration in MEMS-LSI Multichip Module

Cited by 24 publications

References 17 publications

(Invited) Self-Assembly Based Multichip-to-Wafer Bonding Technologies for 3D/Hetero Integration

(Invited) Self-Assembly Based Multichip-to-Wafer Bonding Technologies for 3D/Hetero Integration

3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration

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