A case study in signal processing microprogramming using the URPR software pipelining technique

Abstract

There are a growing number of micro-architectures that employ pipelined array units for high-speed floating point applications. To obtain the performance required in such ap plications, effective loop optimization is crucial. The loop optimization problem for micro-architectures with pipelined processing units is similar to the problem of array processor loop optimization.The URPR method has been proven to be an effective, low-complexity approach to optimizing loops in array processor programs, so we conducted a case study of the method applied to a representative pipelined microarchitecture based on the AIUD29500 chip family. The results of applying two LJRPR compaction algorithms and a new compaction algorithm to the 29500-based micr~architecture are presented. With the new compaction algorithm, we were able to realize microcode as efficient as the complex microcode manually derived by AMD.

A loop optimization technique based on scheduling table

“…In [9] and [8] a loop optimization algorithm called URPR (Unrolling, Pipelining and Rerolling) takes the value N = [L/D] as the number of unrolled iterations, where L is the loop body length, and D the inter-body distance (maximum data dependent distance between any two microoperations in two adjacent unrolled iterations). N is here independent on the resource usage of iterations.…”