The paper demonstrates the advantages of having two processors in the node of a distributed memory architecture, one for computation and one for communication. The architecture of such a dual-processor node is discussed. To exploit fully the potential for parallel execution of computation threads and communication threads, a novel, compiler-optimized IPC mechanism allows for an unbuffered no-wait send and a prefetched receive without the danger of semantics violation. It is shown how an optimized parallel operating system can be constructed such that the application processor's involvement in communication is kept to a minimum while the utilization of both processors is maximized. The MANNA implementation results in an effective message start-up latency of only 1...4 microseconds. It is also shown how the dual-processor node is utilized to efficiently realize virtual shared memory.
The sustained performance of superscalar microprocessors amounts to only a fraction of their peak performance rating. In parallel computers realized with them this discrepancy is even more dramatic. Reaching a satisfactory sustained performance for the single processor is mainly a compiler problem. The sustained performance of parallel computers depends also on other components of the architecture such as the interconnect and the operating system. In the paper it is shown how through a combination of innovative architectural solutions the sustained perfoimance of a distributed memory parallel computer can be significantly improved.The key to effective latency hiding by overlapping communication and computation is the operating system. The programmability of such architectures can be enhanced by providing the programmer with parallelizing compilers and/or a global address space provided by virtual shared memory.
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