A case for dynamic pipeline scaling

Koppanalil, Jinson; Ramrakhyani, Prakash; Desai, Sameer; Vaidyanathan, Anu; Rotenberg, Eric

doi:10.1145/581631.581632

Cited by 17 publications

(10 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, there is a huge concerns for future scaling due to advancement in process technologies. The energy reduction techniques are investigated and some studies on the variable stage pipelining and alternative for existing DVFS techniques have been conducted in [3,14,15]. However, these studies focused on fixed pipeline depth during the program execution.…”

Section: Related Workmentioning

confidence: 99%

“…Using such pipeline depth may be efficient for certain programs, but may also lead to optimal pipeline depth for other programs with different behaviors. In [14], it is argued that deactivating the pipeline stages and using a shallow pipeline can help reducing the processor's power consumption. Most existing representative schemes for reducing the processor's power consumption are localized and often application specific.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

An energy-delay product study on chip multi-processors for variable stage pipelining

Saravanan

Anpalagan

Woungang

2015

Hum. Cent. Comput. Inf. Sci.

View full text Add to dashboard Cite

Power management is a major concern for computer architects and system designers. As reported by the International Technology Roadmap for Semiconductors (ITRS), energy consumption has become one of the most dominant issues for the semiconductor industry when the size of transistors scales down from 22 to 11 nm nodes. In this regard, current existing techniques such as dynamic voltage scaling, clock gating, and the Complementary metal-oxide semiconductor technology have shown their physical limits; therefore, scaling will no longer be a valid strategy for achieving power-performance improvement. To overcome this critical issue in energy-efficient processor design, there is a clear demand for alternative solution. In this paper, an approach that provides a promising solution for energy reduction is proposed, by using a micro-architectural technique referred to as variable stage pipelining, which can be further validated and extended to different application domains such as mobile and desktop. An analytical model for evaluating the relationship between the number of cores and the pipeline stage depth in a chip multi-processor is also proposed, based on which the optimal pipeline depth for various metrics are calculated.

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

An energy-delay product study on chip multi-processors for variable stage pipelining

Saravanan

Anpalagan

Woungang

2015

Hum. Cent. Comput. Inf. Sci.

View full text Add to dashboard Cite

show abstract

“…To achieve such requirement, we have proposed a variable stages pipeline (VSP) technique [4][5][6][7] that is similar technique to dynamic pipeline scaling (DPS) [12] and pipeline stage unification (PSU) [8][9][10][11]. VSP processor dynamically varies the depth of the pipeline stages and clock frequency according to the workload of the processor.…”

Section: Introductionmentioning

confidence: 99%

Energy Optimization using Fine-Grain Variable Stages Pipeline Processor Chip

Nakabayashi

Sasaki

Nakamura

et al. 2013

IJNC

View full text Add to dashboard Cite

Increased energy consumption in processors caused by performance enhancement has recently become a critical problem. Many current processors employ dynamic voltage and frequency scaling (DVFS) which dynamically lowers the supply voltage and clock frequency in order to reduce energy consumption. However, it is difficult to deliver fine-grain energy optimization by using DVFS. Since a voltage regulator takes a long time for scaling the voltage and charging/discharging a power line has a large energy overhead, the useful interval of DVFS is limited to coarse-grain. To optimize energy consumption at fine-grain interval, we have proposed a variable stages pipeline (VSP) processor. VSP reduces energy consumption by dynamically varying the pipeline depth to suitable pipeline depth according to behavior of a running program. VSP can obtain finer-grained energy reduction than DVFS because pipeline scaling only requires a small overhead. In this paper, we fabricated a VSP processor chip using 180 nm technology and evaluated energy consumption of the chip. We present that the fabricated VSP chip dynamically varies the pipeline depth while a program is running and reduces the energy consumption at shorter interval than DVFS. We also analyze how to optimize the energy consumption according to system demand. Our analysis result shows that the VSP can adjust the energy consumption in the same manner for diverse program phases.

show abstract

“…However, Shimada et al [1] and Koppanalil et al [2] have presented a different method, which is called pipeline stage unification (PSU). Its main purpose is to reduce the processor's energy consumption via inactivating and bypassing pipeline registers and thus using shallow pipelines during the program execution.…”

Section: Introductionmentioning

confidence: 99%

A Dynamic Control Mechanism for Pipeline Stage Unification by Identifying Program Phases

Miwa

Shimada

et al. 2008

IEICE Transactions on Information and Systems

View full text Add to dashboard Cite

SUMMARY Recently, a method called pipeline stage unification (PSU) has been proposed to reduce energy consumption for mobile processors via inactivating and bypassing some of the pipeline registers and thus adopt shallow pipelines. It is designed to be an energy efficient method especial for the processors under future process technologies. In this paper, we present a mechanism for the PSU controller which can dynamically predi a suitable configuration based on the program phase detection. Our resul show that the designed predictor can achieve a PSU degree prediction a curacy of 84.0%, averaged from the SPEC CPU2000 integer benchmark With this dynamic control mechanism, we can obtain 11.4% Energy-Dela Product (EDP) reduction in the processor that adopts a PSU pipeline, co pared to the baseline processor, even after the application of complex cloc gating.

show abstract

A case for dynamic pipeline scaling

Cited by 17 publications

References 0 publications

An energy-delay product study on chip multi-processors for variable stage pipelining

An energy-delay product study on chip multi-processors for variable stage pipelining

Energy Optimization using Fine-Grain Variable Stages Pipeline Processor Chip

A Dynamic Control Mechanism for Pipeline Stage Unification by Identifying Program Phases

Contact Info

Product

Resources

About