A Dynamic Control Mechanism for Pipeline Stage Unification by Identifying Program Phases

Abstract

SUMMARY Recently, a method called pipeline stage unification (PSU) has been proposed to reduce energy consumption for mobile processors via inactivating and bypassing some of the pipeline registers and thus adopt shallow pipelines. It is designed to be an energy efficient method especial for the processors under future process technologies. In this paper, we present a mechanism for the PSU controller which can dynamically predi a suitable configuration based on the program phase detection. Our resul show that the designed predictor can achieve a PSU degree prediction a curacy of 84.0%, averaged from the SPEC CPU2000 integer benchmark With this dynamic control mechanism, we can obtain 11.4% Energy-Dela Product (EDP) reduction in the processor that adopts a PSU pipeline, co pared to the baseline processor, even after the application of complex cloc gating.

Energy Optimization using Fine-Grain Variable Stages Pipeline Processor Chip

“…To achieve the requirements, Shimada, et.al. propose PSU [8][9][10][11], Koppanalil,et.al. propose DPS [12] and we propose VSP [4][5][6][7].…”

“…To achieve such requirement, we have proposed a variable stages pipeline (VSP) technique [4][5][6][7] that is similar technique to dynamic pipeline scaling (DPS) [12] and pipeline stage unification (PSU) [8][9][10][11]. VSP processor dynamically varies the depth of the pipeline stages and clock frequency according to the workload of the processor.…”

“…Therefore, fine-grained energy optimization is possible if VSP processor changes the pipeline depth to a suitable pipeline depth using a fine-grain controller. Some controllers for changing pipeline depth have been proposed to dynamically control the pipeline depth [10,11]. As a pipeline depth controller to achieve highly energy-efficient computing, we have proposed a fine-grain controller that predicts a suitable pipeline depth at several tens of clock cycles and have demonstrated the effectiveness of our controller using SimpleScalar [13] processor simulator [6].…”

A Fine-Grained Runtime Power/Performance Optimization Method for Processors with Adaptive Pipeline Depth

“…Methods in [11][12][13] are effective to detect shifts of workload behaviors while their accurate but complex analyzing procedures are expected to be covered by a millisecond-level control interval. Another previously proposed signature history table based workload analyzer [5] will require a period of 50 clock cycles to get the program interval clustering results. When the granularity shrinks to a time slice of less than 100 cycles, the relatively complex method can no longer be applicable.…”

“…Meanwhile, this final averaged EDP result is only 0.14% larger than the theoretically idealized execution, in which the processor is instructed from the statistical profiling data. This EDP reduction is slightly better than the predictor using signature history table (SHT) to identify the program phases [5] . A detailed analysis indicates that the fine-grained analyzer has the following major advantages, as compared to the SHTbased method:…”