A Fine-Grained Runtime Power/Performance Optimization Method for Processors with Adaptive Pipeline Depth

Abstract

Recently, a method known as pipeline stage unification (PSU) has been proposed to alleviate the increasing energy consumption problem in modern microprocessors. PSU achieves a high energy efficiency by employing a changeable pipeline depth and its working scheme is eligible for a fine control method. In this paper, we propose a dynamic method to study fine-grained program interval behaviors based on some easy-to-get runtime processor metrics. Using this method to determine the proper PSU configurations during the program execution, we are able to achieve an averaged 13.5% energydelay-product (EDP) reduction for SPEC CPU2000 integer benchmarks, compared to the baseline processor. This value is only 0.14% larger than the theoretically idealized controlling. Our hardware synthesis result indicates that the proposed method can largely decrease the hardware overhead in both area and delay costs, as compared to a previous program study method which is based on working set signatures.

Energy Optimization using Fine-Grain Variable Stages Pipeline Processor Chip

“…To achieve the requirements, Shimada, et.al. propose PSU [8][9][10][11], Koppanalil,et.al. propose DPS [12] and we propose VSP [4][5][6][7].…”

“…However, interval of changing pipeline depth is the same as DVFS, and so fine-grained energy reduction cannot be obtained. Yao proposes a fine-grain pipeline depth controller for PSU [11] which is similar to our approach one year after we propose, but combining with DVFS is not proposed.…”

“…To achieve such requirement, we have proposed a variable stages pipeline (VSP) technique [4][5][6][7] that is similar technique to dynamic pipeline scaling (DPS) [12] and pipeline stage unification (PSU) [8][9][10][11]. VSP processor dynamically varies the depth of the pipeline stages and clock frequency according to the workload of the processor.…”

“…Therefore, fine-grained energy optimization is possible if VSP processor changes the pipeline depth to a suitable pipeline depth using a fine-grain controller. Some controllers for changing pipeline depth have been proposed to dynamically control the pipeline depth [10,11]. As a pipeline depth controller to achieve highly energy-efficient computing, we have proposed a fine-grain controller that predicts a suitable pipeline depth at several tens of clock cycles and have demonstrated the effectiveness of our controller using SimpleScalar [13] processor simulator [6].…”

Design and evaluation of fine‐grain‐mode transition method based on dynamic memory access analysing for variable stages pipeline processor

“…2 Variable stages pipeline processor VSP technique is similar to pipeline stage unification (PSU) [5][6][7][8][9] and dynamic pipeline scaling (DPS) [10] but is more energy efficient. The basic idea common to PSU, DPS and VSP is shown in Fig.…”