A bottom-up approach for System-On-Chip reliability

Huard, V.; Ruiz, N.; Cacho, F.; Pion, E.

doi:10.1016/j.microrel.2011.07.086

Cited by 24 publications

(17 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, assuming a DC BTI stress may be too pessimistic: a typical CMOS circuit usually switches during operation, and exhibits an AC BTI stress (i.e., transistors experience alternate BTI stress and recovery phases). The measurement results in [10] and [11] show that the amount of BTI degradation is not sensitive to stress duty cycle (i.e., the ratio of total stress time to total operating time) when the duty cycle ranges from 20% to 80%. This means that we can approximate the BTI degradation in a typical CMOS circuit by assuming an AC BTI stress with 50% duty cycle.…”

Section: B Worst-case Bti Degradationmentioning

confidence: 99%

“…As technology nodes advance, bias temperature instability (BTI) is a major aging mechanism, particularly in sub-32 nm CMOS technology. The BTI effect increases the threshold voltage of a MOS transistor, resulting in a time-dependent timing degradation in very large scale integrated (VLSI) circuits [11], [13]. It is mandatory to consider the BTI effect in modern timing signoff recipes-via 10-year timing libraries, flat margin, etc.-to ensure that circuits will operate correctly over their entire lifetimes.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

On Aging-Aware Signoff for Circuits With Adaptive Voltage Scaling

Chan

Kahng

2014

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

Abstract-Transistor aging due to bias temperature instability (BTI) is a major reliability concern in sub-32 nm technology. To compensate for aging, designs now typically apply adaptive voltage scaling (AVS) to mitigate performance degradation by elevating supply voltage. Since varying the supply voltage also causes the BTI degradation to vary over lifetime, this presents a new challenge for margin reduction in the context of conventional signoff methodology, which characterizes timing libraries based on transistor models with pre-calculated BTI degradations for a given IC lifetime. In this paper, we study the conditions under which a circuit with AVS requires additional timing margin during signoff. Then, we propose two heuristics for chip designers to characterize an aging-derated standard-cell timing library that accounts for the impact of AVS during signoff. According to our experimental results, this aging-aware signoff approach avoids both overestimation and underestimation of aging-either of which results in power or area penalty-in AVS-enabled systems. Further, we compare circuits implemented with the aging-aware signoff method based on aging-derated libraries versus those based on a flat timing margin. We demonstrate that the flat timing margin method is more pessimistic, and that the pessimism can be mitigated by AVS.

show abstract

Section: B Worst-case Bti Degradationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

On Aging-Aware Signoff for Circuits With Adaptive Voltage Scaling

Chan

Kahng

2014

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

show abstract

“…However, assuming a DC BTI stress may be too pessimistic: a typical CMOS circuit usually switches during operation, and exhibits an AC BTI stress (i.e., transistors experience alternate BTI stress and recovery phrases). The measurement results in [6] and [7] show that the amount of BTI degradation is not sensitive to stress duty cycle (i.e., the ratio of total stress time to total operating time) when the duty cycle ranges from 20% to 80%. This means that we can approximate the BTI degradation in a typical CMOS circuit by assuming an AC BTI stress with 50% duty cycle.…”

Section: B Worst-case Bti Degradationmentioning

confidence: 99%

“…The BTI effect increases the threshold voltage (|V t |) of a MOS transistor, resulting in a time-dependent timing degradation in very large scale integrated (VLSI) circuits [8] [7]. It is mandatory to consider the BTI effect in modern timing signoff recipes -via 10-year timing libraries, flat V DD margin, etc.…”

Section: Introductionmentioning

confidence: 99%

Impact of Adaptive Voltage Scaling on Aging-Aware Signoff

Chan¹,

Chan²,

Kahng³

2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

View full text Add to dashboard Cite

Abstract-Transistor aging due to bias temperature instability (BTI) is a major reliability concern in sub-32nm technology. Aging decreases performance of digital circuits over the entire IC lifetime. To compensate for aging, designs now typically apply adaptive voltage scaling (AVS) to mitigate performance degradation by elevating supply voltage. Varying the supply voltage of a circuit using AVS also causes the BTI degradation to vary over lifetime. This presents a new challenge for margin reduction in conventional signoff methodology, which characterizes timing libraries based on transistor models with pre-calculated BTI degradations for a given IC lifetime. Many works have separately addressed predictive models of BTI and the analysis of AVS, but there is no published work that considers BTI-aware signoff that accounts for the use of AVS during IC lifetime. This motivates us to study how the presence of AVS should affect aging-aware signoff. In this paper, we first simulate and analyze circuit performance degradation due to BTI in the presence of AVS. Based on our observations, we propose a ruleof-thumb for chip designers to characterize an aging-derated standardcell timing library that accounts for the impact of AVS. According to our experimental results, this aging-aware signoff approach avoids both overestimation and underestimation of aging -either of which results in power or area penalty -in AVS enabled systems.

show abstract

“…The design flow and related algorithms have been treated in other approaches. However, only simple gates have been used in the aging evaluation [7] or the adopted standard cell libraries require previous and complete characterization [11]. At gate level, there are techniques that add a time slack margin to compensate the degradation by upsizing the transistors width [8], whereas other methods focus on the intrinsic robustness of transistor network arrangement [9].…”

Section: Introductionmentioning

confidence: 99%