A 900-MHz 29.5-dBm 0.13-μm CMOS HiVP Power Amplifier

A Three-Stage Inverter-Based Stacked Power Amplifier in 65 nm Complementary Metal Oxide Semiconductor Process

“…In stacked transistors, drain voltage swings are added in phase so that a high voltage swing on the drain of the topmost transistor, that is the output of the PA, could be achieved while voltage swings across terminals of each transistor in the stacked ladder is lower than certain specified breakdown voltages. 4,5,[19][20][21][22][23][24] Apart from lowering the voltage stress on individual transistors, stacked PAs also have other advantages over conventional PA topologies. A PA composed of N stacked transistors has constant input impedance with increasing stacked devices 5,21) and its optimum load is N times higher than that of a single transistor, making it possible to increase the output impedance even up to 50 , all resulting in an improved bandwidth and a better efficiency compared with a conventional PA in which N devices are connected in parallel.…”

Monolithic wideband linear power amplifier with 45% power bandwidth using pseudomorphic high-electron-mobility transistors for long-term evolution application

“…The stacked-FET approach has been very effective in delivering high power for broadband operation since the optimum output load impedance can be adjusted through the bias condition. [18][19][20][21][22] With the proper adjustment of the feedback capacitance, we managed to implement a linear PA with a power bandwidth of 45% for LTE applications. Figure 1 shows the schematic of the designed linear PA for LTE applications.…”