This work proposes a micro electro mechanical systems (MEMS)-based digitally controlled solenoid-inductor. The inductor is fabricated by using a MEMS process. 2-bit tuning characteristics are measured, and tuning linearity and Q-factor degradation due to switching loss are discussed. The linear inductance tuning from 1.7 to 2.2 nH was achieved at 2 GHz. A Q-factor of more than ten was observed in the frequency range of 1.2 to 7.4 GHz. The validity of the proposed inductor was confirmed by investigating the effect of switch resistance.
To determine a micro electro mechanical systems (MEMS) inductor configuration that gives large inductance variations and high Q-factors, air-suspended MEMS inductor configurations are studied: (a) an inductor with two angularly meandered lines, (b) a solenoid inductor with a pair of movable shields, (c) a planar spiral inductor with a patterned shield of different areas, and (d) a planar spiral inductor with a metallic frame of different sizes. The configuration of (a) is shown to give a large inductance variation of 115%. However, its Q-factor is only about 10, and difficulties in fabrication are also expected. The configuration of (b) could be a reasonable engineering solution. The inductance variation is 67%, and the maximum Q-factor is over 22. The solenoidal inductor configuration is thus considered suitable for realizing an RF MEMS variable inductor with large inductance variations and high Q-factors.
A three-stage inverter-based stacked power amplifier (PA) in complementary metal oxide semiconductor (CMOS) process is proposed to overcome low breakdown voltage problem of scaled CMOS technologies. Unlike previous reported stacked PAs which radio frequency choke (RFC) was inevitable, we proposed stacked nMOS and pMOS transistors which effectively eliminates use of RFC. By properly setting self-biased circuits' and transistors' parameters, output impedance could reach up to 50 Ω which together with not employing the RFC makes this topology very appealing for the scalable PA realization. As a proof of concept, a three-stage PA using 65 nm CMOS technology is implemented. With a 6 V power supply for the third stage, the fabricated PA shows a small-signal gain of 36 dB, a saturated output power of 16 dBm and a maximum power added efficiency of 10% at 1 GHz. Using a 7.5 V of power supply, saturated output power reaches 18 dBm. To the best of our knowledge, this is the first reported inverter-based stacked PA.
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