A 8 mW 72 dB ΣΔ-modulator ADC with 2.4 MHz BW in 130 nm CMOS

Bock, Maarten De; Rombouts, Pieter

doi:10.1007/s10470-011-9663-0

Cited by 3 publications

References 19 publications

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A 10-MHz multi-bit MASH delta–sigma modulator with analog summing interstage

Wang

Jung

Roh

2015

Analog Integr Circ Sig Process

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This paper presents an improved 4-bit twostage multi-stage noise shaping (MASH) delta-sigma modulator (DSM). The two-stage MASH DSM utilizes the second-order chain of cascade of integrators with feedforward (CIFF) and the cascade of integrators with distributed feedback (CIFB) architectures for the first and second stages, respectively. The 4-bit CIFF requires an active adder, which is conventionally implemented with a highbandwidth high-swing amplifier. In the proposed DSM, the active adder is eliminated and the adder-less integrator is applied in the first stage of the MASH DSM. The first stage quantization noise, which is fed to the second stage, is conventionally extracted from the analog input and digital output of the quantizer in the first stage. The number of quantizer digital output paths increases exponentially with the quantization bit number. A large number of DAC feedback paths in the interstage is avoided by proposing a new interstage topology based on analog summing to derive the first stage quantization noise in the analog domain. The prototype DSM is fabricated in a 0.11-lm CMOS process. When operating from a 1.2-V supply, the modulator achieves 67.8-dB peak SNDR, while consuming 25 mW, with an OSR of 8 at a 160-MHz sampling frequency.

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A 10-MHz multi-bit MASH delta–sigma modulator with analog summing interstage

Wang

Jung

Roh

2015

Analog Integr Circ Sig Process

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A double-sampling cross noise-coupled Sigma Delta modulator with a reduced amount of opamps

Bock

Rombouts

2013

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

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Calibration of DAC Mismatch Errors in $\Sigma\Delta$ ADCs Based on a Sine-Wave Measurement

Bock

Xing

Weyten

et al. 2013

IEEE Trans. Circuits Syst. II

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Abstract-We present an off-line calibration procedure to correct the non-linearity due to DAC mismatch in multi-bit Σ∆-modulation A/Dconverters. The calibration uses a single measurement on a sinusoidal input signal, from which the DAC-errors can be estimated. The main quality of the calibration method is that it can be implemented completely in the digital domain (or in software) and does not intervene in any way in the analog modulator circuit. This way, the technique is a powerful tool for verifying and debugging designs. Due to the simplicity of the method it may also be a viable approach for factory calibration.

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A 8 mW 72 dB ΣΔ-modulator ADC with 2.4 MHz BW in 130 nm CMOS

Cited by 3 publications

References 19 publications

A 10-MHz multi-bit MASH delta–sigma modulator with analog summing interstage

A 10-MHz multi-bit MASH delta–sigma modulator with analog summing interstage

A double-sampling cross noise-coupled Sigma Delta modulator with a reduced amount of opamps

Calibration of DAC Mismatch Errors in $\Sigma\Delta$ ADCs Based on a Sine-Wave Measurement

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