A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control

Hong, Hyeok-Ki; Kim, Wan; Park, Sun‐Jae; Choi, Michael; Park, Ho‐Jin; Ryu, Seung‐Tak

doi:10.1109/cicc.2012.6330609

Cited by 30 publications

(29 citation statements)

References 5 publications

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“…The following bit decisions in phase P 3 are made with a 16/512 V REF * reference step size, and with ±12/512 V REF * redundancies. Such redundancies of ±12 LSBs in between phases P 2 and P 3 correct errors arising from noise and hardware errors of 4). For an analogous reason, redundancies of ±2 LSBs are given in between P 4 and P 5 , and in between P 5 and P 6 to increase robustness against errors in 3).…”

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confidence: 97%

“…Similarly, in phase P 2 , redundancies of ±40/512 V REF * are inserted in the upper and the lower regions of the decision range, drawing a reference step size of 40/512 V REF * for another 2.6b decision. After phase P 2 , 4) are retired from operations. The following bit decisions in phase P 3 are made with a 16/512 V REF * reference step size, and with ±12/512 V REF * redundancies.…”

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confidence: 99%

“…Thus, to realize high-speed and high-resolution ADCs with TI structures, it is important to alleviate the calibration burden by choosing a suitable number of power-efficient high-speed single channels. Previously reported CDAC-based 2b/cycle structures [2][3][4][5] made contributions in realizing high-speed single-channel ADCs [2][3][4] with high resolution [5] by using additional capacitive DACs and modified switching logic. The power overhead and the complexity of the additional logic and DACs for 2b/cycle implementations have been of trivial concern for low resolution ADCs.…”

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confidence: 99%

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A 2.6b/cycle-Architecture-Based 10b 1.7GS/s 15.4mW 4x-Time-Interleaved SAR ADC with a Multistep Hardware-Retirement Technique

Hong

Kang

et al. 2015

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers

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With the growing interest in time-interleaved (TI) structures, the conversion rates of ADCs have greatly improved, which has inevitably increased power consumption. Despite the advantages of TI structures, power consumption is increased due to the stricter matching requirements between channels; in some cases, >50% of total power is for calibration purposes [1]. Thus, to realize high-speed and high-resolution ADCs with TI structures, it is important to alleviate the calibration burden by choosing a suitable number of power-efficient high-speed single channels. Previously reported CDAC-based 2b/cycle structures [2][3][4][5] made contributions in realizing high-speed single-channel ADCs [2-4] with high resolution [5] by using additional capacitive DACs and modified switching logic. The power overhead and the complexity of the additional logic and DACs for 2b/cycle implementations have been of trivial concern for low resolution ADCs. However, as resolution increases, the complexity of such circuits becomes considerable, with power taking up a big share of the total. In this paper, a multi-step hardware-retirement (MSHR) technique, which disables low-accuracy hardware blocks of scaled sizes with the requirement relaxations from redundancies in an advancement to the reconfiguration scheme in [5], is reported to alleviate the overhead of additional logic and DACs for ADCs, requiring high resolutions. A low-power 2.6b/cycle-based SAR ADC architecture is presented as a proof of concept. Figure 26.7.1 shows a block diagram of the single-end equivalent 10b SAR ADC with 2.6b/cycle architecture. The SAR ADC includes three DACs (SIG-DAC, REF-DAC1, REF-DAC2) and five comparators (CMP0-4). The sizes of REF-DAC(1,2) are designed to be 1/4 of SIG-DAC, while those of CMP(0,1,3,4) are set to be 1/4 of the CMP2, respectively, thanks to the implementation of the MSHR technique with redundancies. The overall sizes of DACs and comparators are 1.5 and 2 times the sizes of SIG-DAC and CMP2, respectively, making the hardware compact. REF-DAC(1,2) form decision thresholds for code decisions independent of the input. The capacitor switching operations of REF-DAC(1,2) are merged with the reference switches shared between REF-DAC1 and REF-DAC2, as shown in Fig. 26.7.1 to simplify control logic. Unlike the REF-DAC, SIG-DAC samples the input and forms a residue after each bit decision.Note that only one SIG-DAC is employed, making the complexity of input-dependent control logic comparable to that of conventional 1b/cycle architectures. A total of 12 cycles are used for a complete single-channel SAR bit decision, where 4 cycles are allocated for sampling purposes. Within the 4 sampling cycles, only 3 cycles are used for pure sampling, while 1 cycle is used to reset SIG-DAC to alleviate the burden of the input driver and to improve sampling linearity. Figure 26.7.2 shows a schematic of SIG-DAC and a descriptive table of the overall structure. Within the total of 536C in SIG-DAC, a total redundancy of 24C is utilized, making the effective referenc...

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confidence: 99%

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A 2.6b/cycle-Architecture-Based 10b 1.7GS/s 15.4mW 4x-Time-Interleaved SAR ADC with a Multistep Hardware-Retirement Technique

Hong

Kang

et al. 2015

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers

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“…It has the inevitable zero-crossing error at the right boundary region. To solve those problems, dummy circuits, calibration engine, and other methods have been published [10][11][12][13][14][15][16]. However, they have a few drawbacks of huge power consumption, large chip area.…”

Section: Circuit Description 1 Odd Number Of Folding Blocksmentioning

confidence: 99%

“…Thus it is a great constraint of high resolution ADCs because of its huge power consumption and chip area. To overcome those problems, folding structure has been continuously studied [4][5][6][7][8][9][10][11][12][13][14][15][16]. However, folding ADCs have an asymmetry error at the boundary conditions, since there is even number of folding blocks [5].…”

Section: Introductionmentioning

confidence: 99%

A 45 nm 9-bit 1 GS/s High Precision CMOS Folding A/D Converter with an Odd Number of Folding Blocks

Lee¹,

Lee²,

Song

2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, a 9-bit 1GS/s high precision folding A/D converter with a 45 nm CMOS technology is proposed. In order to improve the asymmetrical boundary condition error of a conventional folding ADC, a novel scheme with an odd number of folding blocks is proposed. Further, a new digital encoding technique is described to implement the odd number of folding technique. The proposed ADC employs a digital error correction circuit to minimize device mismatch and external noise. The chip has been fabricated with 1.1V 45nm Samsung CMOS technology. The effective chip area is 2.99 mm 2 and the power dissipation is about 120 mW.The measured result of SNDR is 45.35 dB, when the input frequency is 150 MHz at the sampling frequency of 1 GHz. The measured INL is within +7 LSB/-3 LSB and DNL is within +1.5 LSB/-1 LSB.

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An 8-bit 500-MS/s asynchronous single-channel SAR ADC in 65 nm CMOS

Zhang

Zhu

et al. 2015

Analog Integr Circ Sig Process

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A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control

Cited by 30 publications

References 5 publications

A 2.6b/cycle-Architecture-Based 10b 1.7GS/s 15.4mW 4x-Time-Interleaved SAR ADC with a Multistep Hardware-Retirement Technique

A 2.6b/cycle-Architecture-Based 10b 1.7GS/s 15.4mW 4x-Time-Interleaved SAR ADC with a Multistep Hardware-Retirement Technique

A 45 nm 9-bit 1 GS/s High Precision CMOS Folding A/D Converter with an Odd Number of Folding Blocks

An 8-bit 500-MS/s asynchronous single-channel SAR ADC in 65 nm CMOS

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