2015
DOI: 10.1007/s10470-015-0512-4
|View full text |Cite
|
Sign up to set email alerts
|

An 8-bit 500-MS/s asynchronous single-channel SAR ADC in 65 nm CMOS

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2016
2016
2018
2018

Publication Types

Select...
4
1

Relationship

0
5

Authors

Journals

citations
Cited by 5 publications
(1 citation statement)
references
References 11 publications
0
1
0
Order By: Relevance
“…In amidst, several designs have been reported in the recent days, He , et al , which allows the overlapping of the DAC settling with the comparator regeneration reset through speculative DAC outputs and interleaved comparators. It uses two DACs and is very much similar to a two‐channel time‐interleaved architecture [15]. A binary‐search ADC with a reduced comparator count was proposed by Lin , et al , which designated a core idea of reducing the count of decision elements based on the structural modification of [16].…”
Section: Introductionmentioning
confidence: 99%
“…In amidst, several designs have been reported in the recent days, He , et al , which allows the overlapping of the DAC settling with the comparator regeneration reset through speculative DAC outputs and interleaved comparators. It uses two DACs and is very much similar to a two‐channel time‐interleaved architecture [15]. A binary‐search ADC with a reduced comparator count was proposed by Lin , et al , which designated a core idea of reducing the count of decision elements based on the structural modification of [16].…”
Section: Introductionmentioning
confidence: 99%